What is the importance of training in VLSI?

There have been recent doubts and questions about why a fresh engineering graduate and sometimes even experienced engineers have to undergo a paid training/project implementation to be able to land up/shift to a coveted job in core VLSI and closely associated domains like embedded?

Let us try to answer this dilemma/confusion arising in the nubile minds of fresh engineering graduates/recent pass outs.

See we should accept the fact that there exists a huge gap of practical knowledge/hands on expertise between the industry and the academia. This is due to the undeniable fact that what is taught at college level is obsolete or too fundamental to be actually of any help while working at the industry level, whereas the industry expects that whatever manpower they are about to hire will be well versed with the basic concepts and some knowledge about relevant tools and that's the reason we have taken this initiative.

Another point to ponder is that in southern part of India, there are some good VLSI centric academic hubs but in this aspect northern India mainly Delhi/NCR is lacking way behind, irrespective of emergence of sizeable VLSI design industry especially in Delhi/NCR. The number of engineering institutions that have mushroomed in northern part of India in the last 10-12 years is phenomenal. Students passing from those colleges are not aware where should go if they want to take VLSI domain as their preferred carer as they and their parents are reluctant to send them to Bangalore etc.

It has been observed that there are some efforts to provide VLSI training in Delhi/NCR but they are focussing only on specific domain- Frontend (mainly design and verification modelling and coding), which equates to showing only one face of the coin and thus misses out on a comprehensive approach, that is a must for turning out industry ready VLSI skilled manpower. So, after analysing the ground realities we decided to kick start initiatives to provide comprehensive VLSI training targeted for engineering students and in fact related academic institutions in Delhi/NCR region.

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World's Tiniest FM Transmitter Made From Graphene

A team led by James Hone and Kenneth Shepard at Columbia University in New York has demonstrated a device built from a strip of graphene that can transmit FM radio signals. The device, the team says, is the smallest FM transmitter yet made. 

Many research groups have built graphene transistors that could be used in future RF circuits such as signal processors. Hone and his colleagues decided to test a different radio application for graphene, by building a moving, vibrating, electromechanical device. The team reckons that such graphene-based nanoelectromechanical systems (NEMS) could be more compact and easier to integrate onto chips than silicon MEMS and quartz devices, which are used today to pick up and filter RF signals in smartphones and other gadgets.

To build a graphene transmitter, the team suspended a 2-4 micrometer-long strip of graphene above a metal electrode. By applying a voltage to the electrode, they could draw the strip of graphene down. The resulting strain altered the strip's resonant frequency, tuning it up much as you might tighten a guitar string. By altering the voltage on the gate, the team found they could use the graphene device to generate a frequency-modulated electromagnetic signal. In a paper published this week in Nature Nanotechnology, they report the device could transmit radio signals at 100 MHz, right in the center of the FM band. 

For an aural demonstration, the team queued up the now classic K-pop song "Gangnam Style" on an iPhone and fed it into one of their graphene devices. They picked up the result on a regular FM radio tuner that Hone had brought in from home.

Nanowire Transistors Could Keep Moore’s Law Alive

Gate-All-Around Transistors: In a new design, the transistor channel is made up of an array of vertical nanowires. The gate surrounds all the nanowires, which improves its ability to control the flow of current. Platinum-based source and drain contacts sit at the top and bottom of the nanowires.

The end of Moore’s Law has been predicted again and again. And again and again, new technologies, most recently FinFETs, have dispelled these fears. Engineers may already have come up with the technology that will fend off the next set of naysayers: nanowire FETs (field-effect transistors).


In these nanodevices, current flows through the nanowire or is pinched off under the control of the voltage on the gate electrode, which surrounds the nanowire. Hence, nanowire FETs’ other name: “gate-all-around” transistors. However, because of their small size, single nanowires can’t carry enough current to make an efficient transistor.


The solution, recent research shows, is to make a transistor that consists of a small forest of nanowires that are under the control of the same gate and so act as a single transistor. For example, researchers at Hokkaido University and from the Japan Science and Technology Agency reported last year inNature a gate-all-around nanowire transistor consisting of 10 vertical indium gallium arsenide nanowires grown on a silicon substrate. Although the device’s electrical properties were good, the gate length—a critical dimension—was 200 nanometers, much too large for the tiny transistors needed to power the microprocessors of the 2020s. 


Now two researchers working in France, Guilhem Larrieu of the Laboratory for Analysis and Architecture of Systems, in Toulouse, and Xiang‑Lei Han of the Institute for Electronics, Microelectronics, and Nanotechnology, in Lille,report the creation of a nanowire transistor that could be scaled down to do the job. It consists of an array of 225 doped-silicon nanowires, each 30 nm wide and 200 nm tall, vertically linking the two platinum contact planes that form the source and drain of the transistor. Besides their narrowness, what’s new is the gate: A single 14-nm-thick chromium layer surrounds each nanowire midway up its length. 


That thickness, the gate length, is the key. “The advantage of an all-around gate allows the creation of shorter gates, without loss of control on the current through the channel,” explains Larrieu. “We demonstrated the first vertical nanowire transistor with such a short gate.” An all-around gate will be a must if gate lengths are to get smaller than 10 nm, he says. In that scheme, “the size of the gate depends only on the thickness of the deposited layer; there is no complicated lithography involved,” he adds. 


The nanowires were of an unusual construction. Unlike with most vertical nanowire transistor prototypes, in which the nano wires are grown upward from a substrate, the French duo created their nanowires by starting out with a block of doped silicon and then etching away material to leave nano pillars. In between the pillars, they deposited an insulating layer to about half the pillars’ height. Then they deposited the 14 nm of chromium and filled the remaining space with another insulating layer. “We tried to make the process completely compatible with current technology used in electronics. No new machines will have to be invented,” says Larrieu. The researchers have plans to try to go below 10-nm gate length, and also to use indium gallium arsenide nanowires because of the better electron mobility.


Kelin Kuhn, director of advanced device technology at Intel’s Hillsboro, Ore., location, agrees that all-around gate structures have some key advantages. Of all the CMOS-style advanced devices, they’re generally expected to provide the best gate control for very short channels, she says. 


Davide Sacchetto, a researcher at the École Polytechnique Fédérale de Lausanne, agrees: “The fabrication of the gate is interesting, and you get a small gate length.” However, the advantage is lost if the nanowires are too long—200 nm in this case—and the channel is only a small part of the total length of the nanowire, he says. “Even a difference of 5 nm would make a huge difference in the drain current.” 


Tags : summer training in VLSI, backend training instiute in vlsi, mtech. Vlsi projects, Vlsi design

World Smallest Transistors Ever Made

In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Feb Center codeveloped a 3 nmtransistor, the world's smallest nanoelectronic device based on conventional technology, called a fin field-effect transistor (FinFET). It is the smallest transistor ever produced.

In 2010, an Australian team announced that they fabricated a single functional transistor out of 7 atoms that measured 4 nm in length.

In 2012 a single atom transistor was fabricated using a phosphorus atom bound to a silicon surface (between two significantly larger electrodes). This transistor could be said to be a 180 pm transistor (the Van der Waals radius of a phosphorus atom); though its covalent radius bound to silicon is likely smaller. Making transistors smaller than this will require either using elements with a smaller atomic radius, or using subatomic particles—like electrons or protons—as functional transistors.

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A first: Stanford engineers build computer using carbon nanotube technology

A team of Stanford engineers has built a basic computer using carbon nanotubes, a semiconductor material that has the potential to launch a new generation of electronic devices that run faster, while using less energy, than those made from silicon chips
.

This unprecedented feat culminates years of efforts by scientists around the world to harness this promising material.

The achievement is reported today in an article on the cover of Nature magazine written by Max Shulaker and other doctoral students in electrical engineering. The research was led by Stanford professors Subhasish Mitra and H.S. Philip Wong.

"People have been talking about a new era of carbon nanotube electronics moving beyond silicon," said Mitra, an electrical engineer and computer scientist, and the Chambers Faculty Scholar of Engineering. "But there have been few demonstrations of complete digital systems using this exciting technology. Here is the proof."

Experts say the Stanford achievement will galvanize efforts to find successors to silicon chips, which could soon encounter physical limits that might prevent them from delivering smaller, faster, cheaper electronic devices.

"Carbon nanotubes (CNTs) have long been considered as a potential successor to the silicon transistor," said Professor Jan Rabaey, a world expert on electronic circuits and systems at UC Berkeley.

But until now it hasn't been clear that CNTs could fulfill those expectations.

"There is no question that this will get the attention of researchers in the semiconductor community and entice them to explore how this technology can lead to smaller, more energy-efficient processors in the next decade," Rabaey said.

Mihail Roco, senior advisor for Nanotechnology at the National Science Foundation, called the Stanford work "an important, scientific breakthrough."

It was roughly 15 years ago that carbon nanotubes were first fashioned into transistors, the on-off switches at the heart of digital electronic systems.

But a bedeviling array of imperfections in these carbon nanotubes has long frustrated efforts to build complex circuits using CNTs. Professor Giovanni De Micheli, director of the Institute of Electrical Engineering at École Polytechnique Fédérale de Lausanne in Switzerland, highlighted two key contributions the Stanford team has made to this worldwide effort.

"First, they put in place a process for fabricating CNT-based circuits," De Micheli said. "Second, they built a simple but effective circuit that shows that computation is doable using CNTs."

As Mitra said: "It's not just about the CNT computer. It's about a change in directions that shows you can build something real using nanotechnologies that move beyond silicon and its cousins."

Why worry about a successor to silicon? Such concerns arise from the demands that designers place upon semiconductors and their fundamental workhorse unit, those on-off switches known as transistors.

For decades, progress in electronics has meant shrinking the size of each transistor to pack more transistors on a chip. But as transistors become tinier they waste more power and generate more heat – all in a smaller and smaller space, as evidenced by the warmth emanating from the bottom of a laptop.

Many researchers believe that this power-wasting phenomenon could spell the end of Moore's Law, named for Intel Corp. co-founder Gordon Moore, who predicted in 1965 that the density of transistors would double roughly every two years, leading to smaller, faster and, as it turned out, cheaper electronics.

But smaller, faster and cheaper has also meant smaller, faster and hotter.

"Energy dissipation of silicon-based systems has been a major concern," said Anantha Chandrakasan, head of electrical engineering and computer science at MIT and a world leader in chip research. He called the Stanford work "a major benchmark" in moving CNTs toward practical use. CNTs are long chains of carbon atoms that are extremely efficient at conducting and controlling electricity. They are so thin – thousands of CNTs could fit side by side in a human hair – that it takes very little energy to switch them off, according to Wong, co-author of the paper and the Williard R. and Inez Kerr Bell Professor at Stanford.

"Think of it as stepping on a garden hose," Wong said. "The thinner the hose, the easier it is to shut off the flow." In theory, this combination of efficient conductivity and low-power switching make carbon nanotubes excellent candidates to serve as electronic transistors.

"CNTs could take us at least an order of magnitude in performance beyond where you can project silicon could take us," Wong said. But inherent imperfections have stood in the way of putting this promising material to practical use.

First, CNTs do not necessarily grow in neat parallel lines, as chipmakers would like.

Over time, researchers have devised tricks to grow 99.5 percent of CNTs in straight lines. But with billions of nanotubes on a chip, even a tiny degree of misaligned tubes could cause errors, so that problem remained.

A second type of imperfection has also stymied CNT technology.

Depending on how the CNTs grow, a fraction of these carbon nanotubes can end up behaving like metallic wires that always conduct electricity, instead of acting like semiconductors that can be switched off.

Since mass production is the eventual goal, researchers had to find ways to deal with misaligned and/or metallic CNTs without having to hunt for them like needles in a haystack.

"We needed a way to design circuits without having to look for imperfections or even know where they were," Mitra said. The Stanford paper describes a two-pronged approach that the authors call an "imperfection-immune design."

To eliminate the wire-like or metallic nanotubes, the Stanford team switched off all the good CNTs. Then they pumped the semiconductor circuit full of electricity. All of that electricity concentrated in the metallic nanotubes, which grew so hot that they burned up and literally vaporized into tiny puffs of carbon dioxide. This sophisticated technique was able to eliminate virtually all of the metallic CNTs in the circuit at once.

Bypassing the misaligned nanotubes required even greater subtlety.

So the Stanford researchers created a powerful algorithm that maps out a circuit layout that is guaranteed to work no matter whether or where CNTs might be askew.

"This 'imperfections-immune design' (technique) makes this discovery truly exemplary," said Sankar Basu, a program director at the National Science Foundation.

The Stanford team used this imperfection-immune design to assemble a basic computer with 178 transistors, a limit imposed by the fact that they used the university's chip-making facilities rather than an industrial fabrication process.

Their CNT computer performed tasks such as counting and number sorting. It runs a basic operating system that allows it to swap between these processes. In a demonstration of its potential, the researchers also showed that the CNT computer could run MIPS, a commercial instruction set developed in the early 1980s by then Stanford engineering professor and now university President John Hennessy.

Though it could take years to mature, the Stanford approach points toward the possibility of industrial-scale production of carbon nanotube semiconductors, according to Naresh Shanbhag, a professor at the University of Illinois at Urbana-Champaign and director of SONIC, a consortium of next-generation chip design research.

'Accelerator on a chip' demonstrated

In an advance that could dramatically shrink particle accelerators for science and medicine, researchers used a laser to accelerate electrons at a rate 10 times higher than conventional technology in a nanostructured glass chip smaller than a grain of rice.

The achievement was reported today in Nature by a team including scientists from the U.S. Department of Energy's (DOE) SLAC National Accelerator Laboratory and Stanford University.

"We still have a number of challenges before this technology becomes practical for real-world use, but eventually it would substantially reduce the size and cost of future high-energy particle colliders for exploring the world of fundamental particles and forces," said Joel England, the SLAC physicist who led the experiments. "It could also help enable compact accelerators and X-ray devices for security scanning, medical therapy and imaging, and research in biology and materials science."

Because it employs commercial lasers and low-cost, mass-production techniques, the researchers believe it will set the stage for new generations of "tabletop" accelerators.

At its full potential, the new "accelerator on a chip" could match the accelerating power of SLAC's 2-mile-long linear accelerator in just 100 feet, and deliver a million more electron pulses per second.

This initial demonstration achieved an acceleration gradient, or amount of energy gained per length, of 300 million electronvolts per meter. That's roughly 10 times the acceleration provided by the current SLAC linear accelerator.

"Our ultimate goal for this structure is 1 billion electronvolts per meter, and we're already one-third of the way in our first experiment," said Stanford Professor Robert Byer, the principal investigator for this research.

Today's accelerators use microwaves to boost the energy of electrons. Researchers have been looking for more economical alternatives, and this new technique, which uses ultrafast lasers to drive the accelerator, is a leading candidate.

Particles are generally accelerated in two stages. First they are boosted to nearly the speed of light. Then any additional acceleration increases their energy, but not their speed; this is the challenging part.

In the accelerator-on-a-chip experiments, electrons are first accelerated to near light-speed in a conventional accelerator. Then they are focused into a tiny, half-micron-high channel within a fused silica glass chip just half a millimeter long. The channel had been patterned with precisely spaced nanoscale ridges. Infrared laser light shining on the pattern generates electrical fields that interact with the electrons in the channel to boost their energy. (See the accompanying animation for more detail.)

Turning the accelerator on a chip into a full-fledged tabletop accelerator will require a more compact way to get the electrons up to speed before they enter the device.

A collaborating research group in Germany, led by Peter Hommelhoff at the Max Planck Institute of Quantum Optics, has been looking for such a solution. It simultaneously reports in Physical Review Letters its success in using a laser to accelerate lower-energy electrons.

Applications for these new particle accelerators would go well beyond particle physics research. Byer said laser accelerators could drive compact X-ray free-electron lasers, comparable to SLAC's Linac Coherent Light Source, that are all-purpose tools for a wide range of research.

Growing Thin Films of Germanium

Researchers have developed a new technique to produce thin films of germanium crystals -- key components for next-generation electronic devices such as advanced large-scale integrated circuits and flexible electronics, which are required for gadgets that move or bend.

Unlike conventional methods, the new approach does not require high temperatures or other crystals to act as seeds to grow the germanium crystal. And, the researchers say, the new method can be used to produce germanium films with a very large area, allowing for more potential applications.

"This is the realization of the dreams of crystal-growth researchers," says Taizoh Sadoh of Kyushu University. "This unique method will open new ways to create advanced flexible electronics."

Sadoh is an author of the paper describing the new work, which appears in the AIP Publishing journal Applied Physics Letters.

Charged particles move through germanium more readily than they do through silicon, making germanium a good material for electronics. In particular, it is a promising material for the thin-film transistors that are needed for flexible electronics. However, for use in flexible electronics, the germanium would have to be grown on malleable materials, which tend to soften at temperatures above 300° Celsius. The challenge, said Sadoh, is to grow germanium at lower temperatures.

Using gold as a catalyst, Sadoh and his colleagues were able to grow germanium crystals at a temperature of about 250° Celsius. They were also able to grow them in such a way that their crystal structure has the proper orientation and electrical properties necessary for technological applications.