HISTOGRAM EQUALIZATION AND ITS ROLE IN IMAGE PROCESSING

In the era of image processing, scientific analysis, digital photography, remote sensing and in visualization, medical image analysis, surveillance system; image enhancement plays a vital role. By enhancement of image noise can be reduced and it can remove artifacts. A special feature of image enhancement is that it can hold all the details of image after enhancement.

As we know contrast enhancement of an image is done by making light colors lighter and dark colors darker at the same time. And this process is done by setting all color components below a specified lower bound to zero, and all color components above a specified upper bound to the maximum intensity. Here various methods of histogram equalization is addressed. Histogram graphically shows the distribution of pixels among grey scale values. Dynamic range of an image can be improved by equalization method. Histogram equalization is an efficient and useful technique.

The intensities will be equally distributed in output image after the process of histogram equalization.

There are some reasons that led to the need of enhancement:

•          bad quality of the used imaging device,
•          lack of expertise of the operator
•         The adverse external conditions or environment condition at the time of capture.

       IMAGE ENHANCEMENT

Processing of images to extract some specific features of an image is called image enhancement. The main motive of image enhancement is to improve the original image for some specific applications. It sharpens or improves image features such as boundaries, or contrast to make a better graphic display, and better analysis

Image enhancement has two categories:

1) Spatial domain method

2) Frequency domain method

Spatial domain method is based on direct manipulation of pixels in an image. Frequency domain method is based on modifying FT of an image.

Enhancement of an image is done by sharpening, noise removal and brightness increment. Unfortunately there is no general theory for determining what ‘good’ image enhancement, when it comes to human perception. If it looks good .it is good!

Operation of image enhancement is shown by given block diagram

 

Operation of Image Enhancement

Histogram equalization is distribution of particular type of data. It plays a vital role in image processing. By histogram equalization we can improve contrast and appearance of an image. Entire spectrum of pixels (0-255) will be stretches by histogram equalization. A histogram that covers all possible values which is used by gray scale is determined as a good histogram. A good histogram tends to have good contrast and the details of an image that may be easily observed.

In particular, the method can lead to better views of bone structure in x-ray images, and to better detail in photographs that are over or under-exposed.

Here some advantage and disadvantage of this method

Advantage: A key advantage of the method is that it is a fairly straight forward technique and an invertible operator. So in theory, if the histogram equalization function is known, then the original histogram can be recovered.

Disadvantage: A disadvantage of the method is that it is indiscriminate. It may increase the contrast of background noise, while decreasing the usable signal.

Histogram equalization is a specific case of the more general class of histogram remapping Methods. These methods seek to adjust the image to make it easier to analyze or improve the visual quality.

As the methods of histogram equalization are histogram expansion, cumulative distributive equalization, par sectioning, odd sectioning, and local area histogram equalization.

Process of histogram equalization using cumulative distribution function have described in given figure.

 

                                                  Process of histogram equalization

 

PhD Thesis in VLSI

Doctor of philosophy is the final degree in any area. It requires a lot of efforts and hard work to achieve this. It starts with selection of a topic which should be recent and lies in your area of interest. If we talk specifically about research in technology then the next step is not straightforward and as simple as studying, collecting data, analyzing and writing the hypothesis. Research in technology requires implementation of work in the form of prototype or actual real time implementation of the idea.

If we narrow down our discussion to research in areas like electronics, electrical, computer science, artificial intelligence , wireless communication and related fields, which are the base of everything in this high-tech world. In these fields researchers have developed applications (aided with technology) for every field ranging from biomedical to aerospace and construction, which were nowhere related to electronics or even current.

As the research fields we are talking about are providing base to the developing world and providing it with reliable technologies which are being used in real time, the work of researcher becomes more wide starting with an idea to the realization of the idea in the real world in form of application or product.

To make a reliable and working model the idea of the VLSI design project ( i.e speech processing application, biomedical monitoring system etc) needs to be implemented and re-implemented, re-tested and improvised. The there are many development cycles and techniques available which eases up the implementation like:

·         Behavioral simulation

·         Software based model

·         Hardware Implementation (ASIC)

·         Programmable hardware (FPGA)

·         Co-simulation

Behavioral simulation is used at initial phase and it is not appropriate for testing the real time behavior of the system in actual environment as it is more close to systems behavior in ideal environment. 

We can simulate the actual environment by using different software models (more like software models of channels used to test communication systems) but its capabilities are also limited to human capability to model the environmental conditions in mathematical equations and models. 

All of us are familiar with ASIC, their high performance and hardwired implementation. These are good for final implementation but not for intermediate stages of implementation and testing. Nothing is better than ASIC for real time testing of analog VLSI circuits. But for digital circuits and DSP applications we have a better option of FPGA (Field Programmable Gate Array). 

The hardware co-simulation is a good idea to test and monitor systems in real time. To get more details about PhD thesis in VLSI you can do online research or contact us.

WHAT IS BODY BIASING AND ITS DIFFERENT METHODOLOGIES?

Body biasing is the change in transistor threshold voltage because of voltage difference between the transistor source and body. As the voltage difference between source and body effect the threshold voltage of any transistor, so body can be considered as a second gate to determine when transistor will turn on or off. Body coefficient “gamma” determines the strength of body effect. Body effect is diminished with transistor scaling, instead transistor body is connected to power (VDD) for p-channel transistor and to ground for n-channel transistor.

Body Bias:

It involves connecting the body of transistor either to ground or power supply. The body biasing can be applied to transistor either by using off-chip (external) source or by using on-chip (internal) source. In on- chip approach, reverse body bias voltage is provided by charge pump circuit and forward bias voltage is provided by voltage divider circuit. In reverse body biasing we apply negative body-to-source voltage to an n-channel transistor which raises transistor threshold voltage but on the other hand make transistor both slower and less leaky. In forward body biasing we apply positive body-to-source voltage to a p-channel transistor which lowers transistor threshold voltage but on the other hand make transistor both faster and leakier.

Body Bias Methodologies:

·         Fixed Body Bias

In this methodology a fixed body bias voltage is applied to all chips in which body bias value is set during design. In power gating transistor a fixed forward bias voltage is applied during the on state to reduce the on-resistance of the transistor switch and a fixed reverse bias voltage is applied during the off state to reduce the remaining leakage in the power-gated block.

·         Adaptive Body Bias

In this methodology different fixed body bias voltage is calibrated at production test. When forward body bias voltage is applied to slow chip it lowers the threshold voltage and speeds up the chip and when reverse bias voltage is applied to a fast chip it increases transistor threshold voltage and reduces the excess leakage current (and leakage power consumption) of the chip.

·         Dynamic Body Bias

In this methodology the body bias voltage is changed multiple times while the chip is operating rather than setting the body bias just once either during design or at production test. This methodology is also used to reduce temperature and aging effects and it will manage power management modes more effective so that it can optimize very low power operation.

Dynamic body bias can adjust the transistor threshold voltage to compensate for changes in the transistor as the product ages and also adjust threshold voltage of transistor to compensate for temperature related changes in the threshold voltage for transistor as the part heats up and cools down, maintaining more uniform power and leakage.

WHAT ARE DIFFERENT CMOS POWER REDUCTION TECHNIQUES?

As the technology continues to scale down to the deep submicron process, leakage power consumption has become a major concern in designing CMOS VLSI circuits because of reduced threshold voltage and device geometry.

MTCMOS (Multiple Threshold CMOS)- It is a variation of CMOS chip technology in which transistors are there with multiple threshold voltages (V_th) for the purpose of reducing delay and power in circuits. In order to minimize clock periods on critical delay paths, low threshold (V_th) devices are used as they switch faster, but the problem with low V_th devices is that they have substantially high leakage power. In order to minimize static leakage power high V_th devices are used on non-critical paths. Sleep Transistors technique is used in MTCMOS for reducing power. When fast switching speed is required than low V_th devices are used. High V_th devices are turned on inactive mode and off in sleep mode.

Fig1: MTCMOS Circuit

Power Gating- In this technique power consumption is reduced, by not passing currents to those blocks that are not in use. In low threshold transistors sub-threshold leakage current is more, so in order to suppress the high subthreshold leakage current, high sub-threshold voltage switches are added between the low threshold voltage logic circuits and the power supply and ground lines. These high threshold voltages power supply and ground switches are controlled by a sleep signal. During active mode, these switches are on, providing virtual power and ground lines for the logic circuits and during standby mode, these switches are off to reduce sub-threshold leakage current.

DTCMOS (Dual Threshold CMOS)- In this technology high threshold transistor are applied on non-critical path to reduce the sub-threshold leakage and performance is maintained by low threshold transistors in critical paths. So no additional transistors are required and performance as well as low power can be achieved simultaneously.