HOW TO SELECT ARCHITECTURE FOR IMAGE PROCESSING ON FPGA

Implementation of real time image processing on serial general purpose processors is hard to achieve. This is due to the limited resources, general purpose architecture and large data set presented by image. For example if we have to perform single operation on every pixel of the 640x480 gray scale frame from input video source at 30 frames per second, it will require the serial processor to perform 1.84 million operations per second excluding the operations required for reading from and writing data to buffers. This demands a very high throughput serial processor (GPP). 

The above stated problem of image processing at real time can be countered by using FPGAs by using their inherent parallelism of hardware which is an advantage over the fetch decode architecture of processor. Along with solutions comes the complexity of implementation. The software algorithms developed for general purpose processors cannot be directly implemented on FPGA and need to be converted to take advantage of parallelism and meet the constraints implied by hardware. There are popular ways to implement software image processing codes in high level languages (HLL) to FPGA.

• Using HLL to HDL compilers
• Manual conversion

The cases where the hardware implementation is functionally equivalent to software implementation, the mapping is easy and compilers can be used efficiently. Sometimes standard algorithm made for software is not compatible for hardware due to reasons like, the implementation requires too many resources or accesses memory in a way which the hardware cannot support. In such cases we need to re write the algorithm in hardware keeping in mind the limitations and constrains of hardware.

The major constraints implied by hardware implementation are:

•  Timing
• Bandwidth
• Resource utilization and conflict 

The affect of these constraints is closely dependent on the processing model adopted for implementation of the application. The general processing models used are: 

• Stream
• Offline
• Hybrid processing

In stream processing the design samples incoming data like raster scan and perform as much operations as possible. In this mode the role of memory is very important and the processing speed is dependent on bandwidth of memory.

Offline processing doesn’t imply much constraints and it is most suitable for direct mapping of software based algorithm. Hybrid processing is mixture of stream and offline processing and the timing constraints re relaxed as the image is sampled at slower rate.

SiliconMentor: Revealing the Story behind its existence

SiliconMentor is a group of young entrepreneurs pledged to innovate in the field of VLSI by instantaneous interpositions in the technology. It was started in way back July 2013. 

Every start up has its own unique story and some key factors that drove them to start their setup and so is behind the existence of SiliconMentor. SiliconMentor emerged with an idea of two brainstorming VLSI engineers straying to find an opportunity to apply their skills both in terms of technology and its commercialization.

Having started in a box like structure as their workspace, their goals and visions changed at every step as they, themselves did not know about their forthcoming journey. Both of them had mesmerizing ideas to give a challenge to the semiconductor industries and sustain in the core world of electronics. 

On the very first day they sat on their seats with a hope to connect themselves with the VLSI aspirants and provide a certified and conceptual training to the B.Tech and M.Tech students. However, they were hopeless before they got engaged in the first research project in VLSI and later the celebrations after the completion of the project were like Indians celebrate after a victory over Pakistan.

Meanwhile, this was the beginning only before they started to convince the people by promising themselves to be the best among all the VLSI engineers having their setups in the Delhi-NCR region of India.

As much as they earned, they spent to fulfill their desires and more than that with a belief in the saying that “Savers are those, who do not know the ways to earn more” and later the time turned its phase and the ball curtailed in their court.

They went on getting the research projects one after the another and became experts to detect and correct the several small as well as giant problems related to the VLSI circuits and architectures. 

As the time snoozed off, so their goal jerked. Ideas were revolving around to become the most innovative research entity in the field of semiconductor but, the path was still in a haze. 

It is often said that “there is a delay but not the denial” and it completely applied on both of them because they delayed the delivery of work but never anticipated the students to a wrong path.

Semiconductor industry demanded mammoth money in the pocket along with the talent in the mind. The talent they had was not enough to traverse the VLSI world. 

Unlike the western governments, Indian government hardly supports the research activities which was also a discouragement for them and still a milestone to cover up.

Colloquial.......................

Fixed Point VS floating Point Number

FIXED POINT ARITHMETIC: 

Fixed point arithmetic is widely used in hardware implementations. Fixed point is a method to describe real numbers (ones with an integer part and a fraction part) using only integer values. Fixed point values are represented using integers divided into integer and fractional parts.

 

Q_m.n notation where m bits for integer portion, n bits for fractional portion and m+n is known as Word Length(WL). Total number of bits N = m+n+1, for signed numbers.

•       Fixed point value can be calculated as:

 Fixed point value= real number * scale

•       Convert from fixed-point back into a real number:

 Real number =fixed point value/scale

•      Convert a real number to fixed point number

m.n	Integer	Decimal	Scale factor
4.8	4	8	2^8=256
8.8	8	8	2^8=256
2.14	2	14	2^14=16384

•          Conversion from fractional to integer value:

Step1: Normalize decimal fractional number to the range determined by the desired Q format.

Step2: Multiply the normalized fractional number by 2ⁿ.

Step3: Round the product to the nearest integer.

Step4: Write the decimal integer value in binary using N bits.

FLOATING POINT NUMBER:

The term floating point is derived from the fact that there is no fixed number of digits before and after the decimal point. In general, floating-point representations are slower and less accurate than fixed-point representations, but they can hold a larger range of numbers. Floating number represented approximately to a fixed number of significant digits and scaled using an exponent; the base for the scaling is normally two, ten or sixteen. A number that can be representing exactly is in the following form:

Significand x base^exponent 

For example: 1.2345=12345 x 10^-4

Floating-point representation is similar in concept to scientific notation. Logically, a floating-point number consists of:

•                      A signed (meaning negative or non-negative) digit string of a given length in a given base or radix). The digit string is referred to as the significand, mantissa, or coefficient. The length of the significand determines the precision to which number can be represented. The radix point position is assumed always to be somewhere within the significand.

•                      A signed integer exponent which modifies the magnitude of the number.

Nearly all hardware and programming languages use floating-point numbers in the same binary formats, which are defined in the IEEE754 standard. The usual formats in floating point are 32 or 64 bits in total length:

Single Precision – In this, total bits are 32, significand bits 23+1 sign, and exponent bits 8.

Double Precision – In this, total bits 32, significand bits 52 + 1 sign, and exponent bits 11.