Procedural Control Blocks in Verilog

There are two types of procedural blocks in Verilog: initial and always. These statements are the two basic statements in behavioral modeling. Both always and initial statement have separate activity flow. Each flow starts at simulation time 0.


Initial statement :  All statements inside an initial statement constitute an initial block. An initial block starts at time 0, executes once at time of simulation, and doesn’t execute again. If there are multiple initial blocks, each block starts to execute concurrently at time 0.


 Always statement : As it name indicates, it execute statements in always block continuously in a loop fashion. All behavioral statements inside an always statement constitute an always block and starts at time 0. An example is a clock generator module that toggles the clock signal every half cycle.
Example:
module clock_gen;
reg clk;
initial clk=0;
always #10 clk=~clk;
endmodule

PROCEDURAL ASSIGNMENT:
Procedural assignments update values of reg, integer, real, or time variable and cannot assign values to nets (wire data types).

Two types of procedural assignment statements:-

Blocking statement : These statements are executed in the order they are specified in a sequential block. In this, evaluation and assignment are done in a single step.

Example:
integer a=10,b=20,c=30;
 initial begin
 b=a+b;   //b=30   
 c=b;     //c=30
 end;

Non–blocking statement : In this evaluation and assignment in two steps. Firstly right hand side is evaluated immediately and secondly assignment to the left hand side is postponed until other evaluations which are currently going on are completed. A <= operator is used to specify non-blocking assignments.

Example:
integer a=10,b=20,c=30;
 initial begin
 b=a+b;    //b=30   
 c=b;       //c=20
 end;

Procedural Control Block (PCB)

Tags :          Procedural control Block,      PCB ,   FGPA,       ASIC,      HDL      VHDL

Author - Hemika Yadav

(Intern at Silicon Mentor)