We
can easily feel the rapid change in the technology day by day. As we all trying
to digitalize everything to make our life much and more simpler. Various
developing companies are trying their best to develop user friendly gazettes
that must be so small as well as cost efficient that can be easily come under
the common man reach. Developers are trying to put lots n lots of components on
small integrated chip. Hence, Developers had introduced a concept of ‘Built-in
Self-Test’, to test the proper functioning of these chips components. So that,
finally when that IC comes in the hand of common man in form of gazette, he can
make its uninterrupted use.
Basically,
concept of Built-In Self-Test came into picture, when an idea of not using an
external circuitry just for testing the proper functioning of all IC components
strikes in developers mind. According to this concept, any external circuit is
not needed to test the IC. We use to develop an algorithm in such a manner,
that will itself check the outputs of a test pattern generator, with this idea,
that on applying that TPG output as an input of any circuit under test,
we’ll get the desired result or not. BIST is not limited up to this only but
also capable of finding our design’s efficiency, in terms of fault coverage,
that how much number of faults our design has detected. Fault refers to those
inputs, on which our CUT doesn’t give desired output.
It’s
very simple approach of BIST, Design for test is developed in which, a
comparator used to detect the fault, by comparing the patterns of faulty CUT
with non faulty or reference CUT. In this sequence, a slight change is done in
the functionality of CUT. Then, finally comparator used to match each bits of
both reference circuit and faulty CUT. Previously knowing the total number of
faults, this DUT can easily find out the fault finding efficiency of
whole design.
 | |
| Basic Architecture of BIST |
Author
- Akash Kumar
(Research
Associate at Silicon Mentor)
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