Friday, January 8, 2016

VLSI Projects List for M.tech Thesis

  1. A Clock less, Multi-Stable, CMOS Analog Circuit.
  2. An Improved Design of Key Analog Circuits in CMOS Image Sensor
  3. Frequency Compensation in Two-Stage Operational Amplifiers for achieving High 3-db Bandwidth.
  4. Circle Equation-Based Fault Modeling Methodfor Linear Analog Circuits.
  5. Indirect Miller Effect Based Compensation in Low Power Two-Stage Operational Amplifiers.
  6. Analog Circuit Design Using Tunnel-fets.
  7. Ultra-Low-Voltage Operation ofCMOS Analog Circuits: Amplifiers,Oscillators, and Rectifiers.
  8. N-Channel Dual-Workfunction-Gate MOSFET forAnalog Circuit Applications.
  9. Steady State Computation and Noise Analysis of Analog Mixed Signal Circuits.
  10. New Possibilities and Trends in Circuit Design for Analog Signal Processing.
  11. Offset Reduction in Operational Amplifiers using Floating Gate Technology and LMS Algorithm.
  12. A  Method  of  Analog  Circuit  Optimization  Using Adjoint  Sensitivity  Analysis
  13. Area and power optimized multipliers with minimum leakage.
  14. Comparison and analysis of combinational circuits using different logic styles.
  15. Combinational circuits without false paths.
  16. Fast 32-bit digital multiplier.
  17. Fully cmos programmable voltage adder/subtractor.
  18. Optimization of combinational logic circuits through decomposition of truth table and evolution of sub-circuits.
  19. Low-power design techniques for high-performance cmos adders.
  20. Variable input delay cmos logic for low power design.
  21. Analysis of metastability performance in digital circuits on flip-flop.
  22. A translinear-based implementation of digital logic gates using only cmos in current-mode.
  23. Optimized power performance and simulation of reversible logic multiplexer.
  24. Vlsi implementation of reduced complexity wallace multiplier using energy efficient cmos full adder.
  25. An improved design of combinational digital circuits with multiplexers using genetic algorithm
  26. Mixed-Signal VLSI Design in 0.5μm Process of Nano-Power Subcompact Mirror Amplifier for Accusensor.
  27. CMOS Current Steering Logic for Low-Voltage Mixed-Signal Integrated Circuits.
  28. A 3.8-ns CMOS 16 x 16-b Multiplier Using Complementary Pass-Transistor Logic.
  29. The Design of A Low-Power Low-Noise Phase Lock Loop.
  30. Ultra-High Bandwidth Fully-Differential Three-Stage Operational Amplifiers in 40nm Digital CMOS.
  31. Wide Output Swing Inverterfed Modified Regulated CASCODE Amplifier for Analog and Mixed-Signal Applications.
  32. A Digital-Based Analog Differential Circuit.
  33. A low open-loop gain, high-PSRR, micro power CMOS amplifier for mixed-signal applications.
  34. Circuit Techniques for CMOS Low-Power High-Performance Multiplier.
  35. An Efficient Mixed-Signal 2.4-ghz Polar PowerAmplifier in 65-nm CMOS Technology.

Friday, July 3, 2015

FPGA Design and Verilog HDL Projects List

1.      FPGA implementation of LDPC bit-flipping algorithm using Co-simulation.
2.      FPGA implementation of LDPC Decoder using min-sum algorithm.
3.      Implementation of AES for image encryption and decryption.
4.      Development and verification of SPI protocol.
5.      Development and verification of PPI protocol.
6.      Audio processing using digital filter using Co-simulation.
7.      Design of single precision (32-bit) Floating point ALU.
8.      Design and implementation of the 128-point FFT processor.
9.      Design and implementation of 16bit RISC Processor.
10.    FPGA implementation of the 12-bit Ternary multiplier.
11.    Design of ECG signal processing and denoising using co-simulation.
12.    Design of low power test pattern generator.
13.    A BIST TPG for Low Power Dissipation and High Fault Coverage
14.    Low-Transition LFSR for BIST-Based Applications
15.    Verilog Implementation of UART with BIST capability
16.    Verilog implementation of RSA cryptography algorithm.
17.    Verilog implementation of 64, 32, 16 and 8 bit CSA.
18.    Design of low power TPG using LP_LFSR for fault coverage.
19.    Design and implementation of the 32-point FFT processor by Folding Transform.
20.    FPGA implementation of the REDEYE detection and correction.
21.    FPGA implementation JPEG 2000 using 2-D DWT .
22.    Hardware implementation JPEG 2000 using DWT.
23.    Hardware implementation of the H.264 encoder for HD Video.
24.    Hardware implementation of the MPEG encoder.
25.    FPGA implementation of Quantization algorithms for multi standard video platform.
26.    FPGA implementation of the motion object detection based on background subtraction.
27.    FPGA implementation of the AES algorithm for reduced cycles.
28.    Design and implementation of the MRI image enhancement and denoising.
29.    Hardware implementation of the ECG (Arrhythmia).
30.    Fault tolerant deflecting router with high fault coverage for ON-Chip network.
31.    BIST implementation of the UART.
32.    Orientation field estimation for the fingerprint enhancement.
33.    Verilog implementation of Reconfigurable router (NOC).
34.    Verilog implementation of Decimal to binary conversion.
35.    Verilog implementation of 3D-DWT.

If you need any suggestion or research guidance for FPGA design & verilog HDL projects then feel free to contact us.

Friday, June 26, 2015

Low Power Digital VLSI Projects List

  • ALU in FINFET
  • VARIABLE TAPER CMOS BUFFER DESIGN
  • Sleepy Keeper Approach for Power Performance Tuning in VLSI Design.
  • 0-9 bit pattern recognition circuits using neural network, 3-bit pattern recognition.
  • An adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage Scalable Standard Cell Library.
  • Lewis grey comparator.
  • 4×4-Bit Array Two Phase Clocked Adiabatic Static CMOS Logic Multiplier with New XOR.
  • Adiabatic Logic Based Low Power Multiplexer and De-multiplexer.
  • Low Power D-latch design using MCML Tri-state Buffers.
  • Ultra Low Power NAND Based Multiplexer and Flip flop.
  • MOS Current Mode Logic Realization of Digital Arithmetic Circuits.
  • 0-0\9 digit pattern recognition circuit using neural network.
  • 6 transistors XOR and XNOR using FINFET.
  • Winner Take All Circuits of O (n) Complexity.
  • Low power adiabatic booth multiplier using Positive feedback adiabatic logic (PFAL).
  • Transmission gate based full adder in deep sub-micron technology.
  • Low power radix-4 booth multiplier using GDI logic.
  • High performance nibble multiplexer using modified adiabatic logic.
  • Sense energy recovery full adder working in sub-threshold region of operation.
  • Clock gated 4-bit Johnson counter using low power JK flip flop.
  • A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs.
  • New Low-Power Techniques: Leakage Feedback with Stack & Sleep Stack with Keeper.
  • Low Power, Delay Optimized Buffer Design using 70 nm CMOS Technology.
  • Clock gated 4-bit Johnson counter using low power JK flip flop.
  • Design of a novel low power 8-transistor 1-bit full adder cell.
If you need any suggestion or research guidance for Low Power Digital VLSI Projects then feel free to contact us.

Analog & Mixed Signal Design Projects List

  •    Common source amplifier.
  •    Flash ADC Architecture using Multiplexers to Reduce a Preamplifier and Comparator Count.
  •    Design of SRAM Cell from (6 transistors-12 transistors).
  •    6 Bit multiplexed based modified Flash Analog to Digital converter.
  •    Over Current protection circuit.
  •    TIQ based ADC.
  •    Low supply Voltage High performance CMOS current mirror.
  •    Low power quad node 10T soft error tolerant SRAM cell for space applications. (at 90nm).
  •    Power reduction technique for low power SRAM’s with high soft error tolerance.
  •    Design of long reset time Power on reset (POR) circuit with Brown out detection.
  •    Design and analysis low power two stage operational amplifiers at 180 nm.
  •    Design and Simulation Difference Types CMOS Phase Frequency Detector for high speed and   low   Jitter PLL.
  •    Switched-current type of hamming neural network system for pattern recognition.
  •    Design of a Low-Voltage Low-Dropout Regulator.

If you need any suggestion or research guidance for Analog & Mixed Signal design projects then feel free to visit us.

Sunday, June 21, 2015

An overview of Research Guidance in PhD

Silicon Mentor is one of the best research entities in India. To make an environment of research we are providing our services in research and development of some of the world most recent burning topics in engineering and technology. Silicon Mentor has expertise in various research domain including Computer Vision, Machine Learning, VLSI, Biomedical Signal Processing and Digital Signal Processing. In the process of research and development we have a unit which provides research guidance to the PhD students. Our research process for PhD projects starts from the specific domain topic selection.



1)    The topic selection is based on either on the student requirement or we suggest them appropriate topic.
2)    After the selection of appropriate topic and research domain we assign our expert team for the support PhD student. This team works with the students on some of the previous work published in SCI indexed journals.
3)    During the review period of the previous work our team starts to generate new idea to modify the previous work.
4)    After the completion of previous work verification we turn our direction of research towards the modification in the previous design or to generate a new idea.
5)    For the implementation of new idea or modification we continuously contact the students and make him understand the new work.
6)    For the required tool training Silicon Mentor runs special class to train the students.
7)    After the modification of the design we do compare the result of the modified design and previous work.
8)    After the verification of complete verification of the result we forward this to next step.
9)    We do also compare analytical and simulative results for the preparation of the proposed method.
10)    After the completion of the all above steps we provide our expert team in the domain of research paper publication.
11)    Our expert team of Research paper publication provides updates about the new conference and journal publication.
12)    We usually suggest our clients to publish their work in IEEE, Springer like publications.
13)    We also help them to publish their work in any of the SCI index journals.

Thus we try to provide best research guidance for PhD thesis and PhD projects. We are in the process of continuous improvement to make our services more convenient in the area of Research and Development. For more information you can contact us.

Tuesday, June 9, 2015

How to make an FPGA Partially Reconfigurable

Partially reconfiguration means changing the FPGA partially or only the selected part of the FPGA is reconfigured. It can be done in two ways:

i)    Module based partial reconfiguration
Partial reconfiguration on the basis of difference

Module based partial reconfiguration:


In module based reconfiguration we reconfigure on the specific module or only by changing a selected module we can do the partially reconfiguration of our FPGA. The portions of the design to be reconfigured are known as reconfigurable modules. Specific properties and specific layout criteria must be met with respect to a reconfigurable module, FPGA design intending to use partial reconfiguration must be planned and laid out with that in mind.

Partial reconfiguration on the basis of difference:


Partial reconfiguration on the basis of difference is a method of making small changes in an FPGA design, such as changing I/O standards, LUT equations, and block RAM content.

Applications:


i)    To lessen power or making the design power-efficient.
ii)    Through the JTRS Program, SDRs are becoming a reality for the defense industries as an effective and necessary tool for communication. SDRs assure the JTRS standard by having both a software-reprogrammable operating environment and the ability to support multiple channels and networks simultaneously.
iii)    Partial reconfiguration is useful in a variety of applications across many industries. The aerospace and defense industries have certainly taken advantage of its capabilities.
iv)    Increased system performance. Although a portion of the design is being reconfigured, the rest of the system can keep on to operate. There is no loss of performance or functionality with unaffected portions of a design.
v)    Hardware sharing. Because partial reconfiguration allows you to run multiple applications on a single FPGA, hardware sharing is realized. Benefits include reduced device count, reduced power consumption, smaller boards, and in particular lower costs.

key steps used in Xilinx to make the FPGA partially Reconfigured:


1: First Create Processor Hardware System.
2: Then Create Software Project.
3: After then Create a Plan ahead Project.
4: Defining a Reconfigurable Partition.
5: Adding Reconfigurable Modules.
6: significant the Reconfigurable Partition Region.
7: Running the Design Rule Checker.
 8: Then Create the First Configuration, Implementing, and Promoting.
9: Then Create Other Configurations, and Implementing.
10: Then Run Partial Reconfiguration to Verify Utility.
11: Generating Bit Files.
12: Creating an Image, and Testing.

Advantages:


There are many advantages to make the FPGA reconfigured. only some from them are following:

I)    To make the device more efficient.
II)    To lessen the LUTs of the design by replacing only specific portion.
III)    To lessen power of the design by replacing only specific portion.
IV)    To lessen the delay of the design by replacing only specific portion or a specific module.




                                                                                                                     author: Rishi Saini
                                                                                                 (Research Associate at SiliconMentor)
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Monday, June 1, 2015

Is It The Right Path To Pursue PhD Research?



PhD research is the highest level of academic research conducted in universities and institutes throughout the World. The methods used to conduct Ph.D. research are sound and the data that results from the research must be unique. There are many techniques has been created such as scientific methodologies have been created to ensure the soundness and uniqueness of doctoral research and to secure continuity in research results. The most often employed methodologies are quantitative methods, qualitative methods, comparative methods and clinical trials.

The world is producing a large number of PhD holders and their number is increasing every year. Therefore in this era how can a normal PhD holder can survive? World’s most population countries India and China producing more than 40,000 PhD every year. Most of the PhD has completed their research in a short duration which results in the quality of the graduates is not consistent. And Most of the PhD remains unemployed.




In our research whenever we think of doing the research we always think of  doing something innovative  which can change the world but when we come for real implementation of the idea we found only few things have done in our PhD research. The few things which done usually during PhD seems to be unique. What should we do? And, how to do? It depends on one’s circumstances but the research should contribute something new in the specific domain. 

Silicon Mentor is a place where many new researchers are working together to make something innovative and unique. These young researchers help the research students to pursue their research with some of the unique methodologies. Silicon Mentor have Expertise in different Domain such as Computer vision , Biomedical Research, Digital Signal Processing, Machine Learning , Low Power VLSI , Mixed Signal VLSI , FPGA implementation.