The historical growth of IC computing power has profoundly changed the way we create process, communicate, and store information. The ability to shrink transistor dimensions every few years. This trend, known as Moore’s law. However, it is projected that in one or two decades, transistor dimensions will reach a point where it will become uneconomical to shrink them any further, which will eventually result in the end of the CMOS scaling.
The ability to scale a transistor’s supply voltage is determined by the minimum voltage required to switch the device between an on- and an off-state. The sub-threshold slope (SS) is the measure used to indicate this property. For instance, a smaller SS means the transistor can be turned on using a smaller supply voltage while meeting the same off current. For MOSFETs, the SS has to be greater than ln (10) × kT/q where k is the Boltzmann constant, T is the absolute temperature, and q is the electron charge. This fundamental constraint arises from the thermionic nature of the MOSFET conduction mechanism and leads to a fundamental power/performance tradeoff, which could be overcome if SS values significantly lower than the theoretical 60-mV/decade limit could be achieved.
Many device types have been proposed that could produce steep SS values, including tunneling field-effect transistors (TFETs), nano electromechanical system (NEMS) devices, ferroelectric-gate FETs, and impact ionization MOSFETs. Several recent papers have reported experimental observation of SS values in TFETs as low as 40 mV/decade at room temperature. These so-called “steep” devices’ main limitations are their low mobility, asymmetric drive current, bias dependent SS, and larger statistical variations in comparison to traditional MOSFETs.
nano electromechanical system (NEMS) devices characterstics
tunneling field-effect transistors (TFETs).
Author - Akash Kumar
(Design Engineer at Silicon Mentor)