Monday, April 20, 2015

Low Power Techniques in the FINFET



Fin type field effect transistors (FINFETs) is a new type of CMOS in VLSI. These are doubled gated device. The two gates of a FINFET can either be shorted or independently controlled for lower leakage. It has lower short channel effects (SCEs) and ideal sub threshold voltage. To make a FINFET, the front oxide is made much thicker than the side oxides in order to effectively deactivate the front gate. We call this device FINFET because the thin channel region stands vertically similar to the fin between the sources and drain regions.

There are different modes of FINFET (a) Short gate (SG) mode (b) Independent gate (IG) mode (c) Low power (LP) mode (d) A hybrid IG/LP-mode.

  1.   SG Mode:In this mode both gate are shorted and we get good control over the channel length
  2.   IG Mode:In this independent signals are provided to the two device gates, this will reduce the number of transistors in the circuit.
  3.   LP mode:In this we are applying a low voltage to n type FINFET and high voltage to P type FINFET.
  4.   Hybrid mode:It is a combination of LP and IG modes.
Different techniques for low power consumption:

a)DTCMOS: This technique reduces standby power by using the P-MOS switch with higher threshold voltage in between power supply and the circuit. It can also use N-MOS switches with higher threshold voltage in between ground and the circuit. This high threshold transistors can operate with high speed and low switching power dissipation. When the circuit is in OFF mode the high threshold transistors are turned OFF causing reduction in the sub-threshold leakage current.

b)Self Controlled Voltage Level(SVL): There are three types of SVL techniques:

  •          Type-1 has an upper SVL circuit, in this we can use single P-MOS switch and n no. of N-MOS switches connected in series. The ON P-MOS connects a power supply and the load circuit in the active mode and the all N-MOS are disconnected and they are in standby mode.
  •          Type-2 has a lower SVL circuit, in which we use single N-MOS switch and n no. of P-MOS switches connected in series. The lower SVL circuit not only supplies 0 to the active-load circuit through the ON N-MOS but also supplies 0 to the standby load circuit through the use of the ON P-MOS.
  •          Type-3 has a combination of lower and upper SVL circuit.When the gate voltage of circuit is kept at 0, the P-MOS is turned ON while the N-MOS is turned OFF. The current is pass through the P-MOS and through the n P-MOS in the lower circuit. When control signal turns to 1 the N-MOS is turned ON and turns OFF P-MOS, power is supplied to the circuit through n N-MOS. This results in a decrease in the sub threshold current of the N-MOS that is the leakage current through the circuit decreases.