HSPICE/PSPICE Training and Projects

SPICE:

The rapid change in the field of electronics engineering is paralleled by programs that use the computer’s increased capabilities in the solution of both traditional and novel problems. With the availability of tools for computer-aided circuit analysis, circuits of great complexity can be designed and analyzed within a shorter time and with less effort compared to the traditional methods. SPICE is a computer-aided simulation program that enables the design and simulation of circuits. SPICE is the acronym for a Simulation Program with Integrated Circuit Emphasis.

Fundamentals of SPICE Programming:

Programming a circuit simulation with SPICE is much like programming in any other computer language: you must type the commands as text in a file, save that file to the computer's hard drive, and then process the contents of that file with a program (compiler or interpreter) that understands such commands.

SPICE is a General- Purpose circuit simulation program for non-linear DC, nonlinear transient and linear AC analysis. Circuits may contain Resistors, capacitors, inductors, mutual inductors, independent voltage and current sources, four types of dependent sources, transmission lines, switches, and several semiconductor devices: including diodes, BJTs, JFETs, MESFETs, and MOSFETs. Circuits with large numbers of all types of components can be simulated.

In PSPICE the program we run in order to draw circuit schematics is called CAPTURE. The program that will let us run simulations and see graphic results is called PSPICE. You can run simulation from the program where your schematic is. There are a lot of things we can do with PSPICE, but the most important things for you to learn are :

1. Design and draw circuits

2. Simulate circuits

3. Analyze simulation results (Probe for older versions)

For this course you will not need the full capacity of CAPTURE. The devices that we will use are resistors, inductors, capacitors and various independent/dependent sources. It is good to know that CAPTURE has extensive symbol libraries and includes a fully integrated symbol editor for creating your own symbols or modifying existing symbols :

The main tasks in CAPTURE are :

1. Creating and editing designs

2. Creating and editing symbols

3. Creating and editing hierarchical designs

4. Preparing your design for simulation.

Tags :  SPICE Training    PSPICE Training       SPICE              SPICE Programming                 HSPICE

 Author- Amresh Kumar Singh

 (Research Associate at SiliconMentor)

Procedural Control Blocks in Verilog

There are two types of procedural blocks in Verilog: initial and always. These statements are the two basic statements in behavioral modeling. Both always and initial statement have separate activity flow. Each flow starts at simulation time 0.


Initial statement :  All statements inside an initial statement constitute an initial block. An initial block starts at time 0, executes once at time of simulation, and doesn’t execute again. If there are multiple initial blocks, each block starts to execute concurrently at time 0.


 Always statement : As it name indicates, it execute statements in always block continuously in a loop fashion. All behavioral statements inside an always statement constitute an always block and starts at time 0. An example is a clock generator module that toggles the clock signal every half cycle.
Example:
module clock_gen;
reg clk;
initial clk=0;
always #10 clk=~clk;
endmodule

PROCEDURAL ASSIGNMENT:
Procedural assignments update values of reg, integer, real, or time variable and cannot assign values to nets (wire data types).

Two types of procedural assignment statements:-

Blocking statement : These statements are executed in the order they are specified in a sequential block. In this, evaluation and assignment are done in a single step.

Example:
integer a=10,b=20,c=30;
 initial begin
 b=a+b;   //b=30   
 c=b;     //c=30
 end;

Non–blocking statement : In this evaluation and assignment in two steps. Firstly right hand side is evaluated immediately and secondly assignment to the left hand side is postponed until other evaluations which are currently going on are completed. A <= operator is used to specify non-blocking assignments.

Example:
integer a=10,b=20,c=30;
 initial begin
 b=a+b;    //b=30   
 c=b;       //c=20
 end;

Procedural Control Block (PCB)

Tags :          Procedural control Block,      PCB ,   FGPA,       ASIC,      HDL      VHDL

Author - Hemika Yadav

(Intern at Silicon Mentor)

What is HDL ?

Hardware description language (HDL) plays a vital role in very large scale integration (VLSI). HDLs looks much like a programming language C.  HDL   is textual description of an electronic circuit or  electronic chip.  In other words HDL is used  to describe hardware in terms of expressions and statements, control structures.  HDL is concurrent (all parts work at the same time)whereas traditional software is sequential. HDL is real time sensitive unlike software.  HDL  also allows for the compilation of an HDL program into a lower level specification of physical electronic components, such as the set of masks used to create an integrated circuit.

 HDL has ability to describe and simulate at behavioural, structural and mixed level. From above description we can say that HDL form an integral part of electronic design automation system,  specially for complex circuits such as microprocessor. Now we will know  more about HDLs. There are two types of HDL which is supported by IEEE. They are VHDL  ( Very high speed integrated circuit HDL) and Verilog HDL. These language are used in electronic devices that do not share computer’s basic architecture.

For high level modeling VHDL is  better while Verilog is better  for gate level modeling and switch level modeling. VHDL is not case sensitive while Verilog is case sensitive. Verilog is similar to C or PASCAL  language while VHDL is similar to ADA programming language in syntax. VHDL is more complex then  verilog. VHDL has the advantage of having a lot of constructs that aid in high level modeling. Verilog is easy to understand and easy  to  design. VHDL is different from Verilog in terms of signal assignment, interface declaration, in RTL assignment.  Verilog is much better then VHDL below the RTL level.  VHDL and Verilog is equivalent for RTL modeling. But the bottom line is that we should know both.

Verilog-HDL

Tags : HDL,  Verilog ,     VHDL ,     RTL ,     FPGA Vs ASIC ,  Verilog Training 

Author - Trisha Jain

(Intern at Silicon Mentor)