Friday, April 24, 2015

Level Shifter: Power Reduction Techniques and its Applications

Level shifters are one of the important components in electronic devices and there common work is to convert the digital signal from one voltage level to other .The major parameters for performance analysis of a level shifter include its power consumption and delay.  These are commonly used circuit component in any multi-voltage electronic system. This approach leads to a design in which different blocks of circuit operate at distinct voltage levels. This factor can be used for enhancement of the circuit operation for minimum energy consumption. A variety of level shifter designs have been designed with single and dual output voltages. Usual shifters have disadvantage of higher power consumption, delay discrepancy and faulty operation at lower supply voltage VddL.

Power Reduction Techniques:

  Capacitive Coupling   -  The basic concept for using this approach is to reduce short circuit current and thus reducing the power consumption. The fast switching characteristic of capacitive coupling reduces the short circuit current during the transition time of input signal. The power can be reduced to about half by implementing this technique.

  Body Biasing Approach – The main feature is using selected body bias where minimum leakage current flows. It is better than bootstrap technique which resulted in delay increment in circuit. This approach limits the power consumption with minimum complexity in design and with slight negotiation in delay parameter.

  Bootstrapping Technique - In this technique, the output node is boosted Up as well as Down by Cboost  capacitor. A bootstrapping switch is used to improve the drivability of pull-up transistors in the level shifter. Furthermore, a pull-down driver is used to have elevated driving capability. Utilizing this approach, it has become possible to reduce the power dissipation keeping along a great performance in low voltage applications.

Power consumption in range of Nano-Watts and Pico-Watts can be achieved in circuit using these techniques.


There are frequent cases in digital electronics where different sections of the system operate from different power supply voltages. A very straightforward example that can illustrates the operation of level shifter is its utility in a circuit that alters the logic levels from the level supplied by one domain to second domain,  like a +5 Volt power supply to a +9 Volt power supply or a +/- 5 Volt dual supply.

1.  One of the very significant applications includes control of Analog Switches where the bipolar signals are necessary and require dual +/- 5 Volt supplies.

2.  A level shifter can be used for shifting the Bus Signals so that different devices operating at different voltages can communicate over the bus.

3.  These are most important block in any Inter-Integrated-Circuit. 

To get more information contact us at: SiliconMentor.

Monday, April 20, 2015

Low Power Techniques in the FINFET

Fin type field effect transistors (FINFETs) is a new type of CMOS in VLSI. These are doubled gated device. The two gates of a FINFET can either be shorted or independently controlled for lower leakage. It has lower short channel effects (SCEs) and ideal sub threshold voltage. To make a FINFET, the front oxide is made much thicker than the side oxides in order to effectively deactivate the front gate. We call this device FINFET because the thin channel region stands vertically similar to the fin between the sources and drain regions.

There are different modes of FINFET (a) Short gate (SG) mode (b) Independent gate (IG) mode (c) Low power (LP) mode (d) A hybrid IG/LP-mode.

  1.   SG Mode:In this mode both gate are shorted and we get good control over the channel length
  2.   IG Mode:In this independent signals are provided to the two device gates, this will reduce the number of transistors in the circuit.
  3.   LP mode:In this we are applying a low voltage to n type FINFET and high voltage to P type FINFET.
  4.   Hybrid mode:It is a combination of LP and IG modes.
Different techniques for low power consumption:

a)DTCMOS: This technique reduces standby power by using the P-MOS switch with higher threshold voltage in between power supply and the circuit. It can also use N-MOS switches with higher threshold voltage in between ground and the circuit. This high threshold transistors can operate with high speed and low switching power dissipation. When the circuit is in OFF mode the high threshold transistors are turned OFF causing reduction in the sub-threshold leakage current.

b)Self Controlled Voltage Level(SVL): There are three types of SVL techniques:

  •          Type-1 has an upper SVL circuit, in this we can use single P-MOS switch and n no. of N-MOS switches connected in series. The ON P-MOS connects a power supply and the load circuit in the active mode and the all N-MOS are disconnected and they are in standby mode.
  •          Type-2 has a lower SVL circuit, in which we use single N-MOS switch and n no. of P-MOS switches connected in series. The lower SVL circuit not only supplies 0 to the active-load circuit through the ON N-MOS but also supplies 0 to the standby load circuit through the use of the ON P-MOS.
  •          Type-3 has a combination of lower and upper SVL circuit.When the gate voltage of circuit is kept at 0, the P-MOS is turned ON while the N-MOS is turned OFF. The current is pass through the P-MOS and through the n P-MOS in the lower circuit. When control signal turns to 1 the N-MOS is turned ON and turns OFF P-MOS, power is supplied to the circuit through n N-MOS. This results in a decrease in the sub threshold current of the N-MOS that is the leakage current through the circuit decreases.

Friday, April 17, 2015

Hardware Co-simulation for Non Memory Mapped Ports using Simulink and System Generator

Hardware or FPGA is a primary requirement for any real time implementation of mathematical algorithms. The main drawback of the process is the limited resources and the interfaces available on the FPGA for the co-simulation process. One of the main highlighted concern is the mapping of the peripheral ports on the FPGA with the algorithm. 

Co-simulation is the best process to use for the real time implementation of the algorithms because the process facilitates the features of the two tools simultaneously. MATLAB is known as the best tool for the implementation of the mathematical algorithms for a number of applications. The other tool System Generator from by the Xilinx is known best for the hardware implementation of the algorithms. 

Both the tools work together simultaneously to real time implementation of the mathematical algorithms on the FPGAs. The complications are their when you want to use the LEDs, Buttons or other output devices. To resolve these problems we manually create the Non Memory Mapped Ports according to the steps given below.

To manually create NMM we need these different Simulink and system generator block sets.
1.       In1
2.       Convert
3.       Gateway In
4.       Out1
5.       Terminator

To generate the library subsystem we have to put these block as in the given fig:1

Fig: 1

The work is almost done we just need to run the given three command on the MATLAB command window after selecting the “Gateway Out” block

>>xlSetNonMemMap(gcbh, 'Xilinx', 'ethernetcosim'); 
>>xlSetPortParams(gcbh, 'IOConstraint', 'NET "pmod0" LOC = U18;');

This command is to map output of the design to the LED of the FPGA. “U18” is the pin location of the LED<0> in our case and can be changed on the basis of different pin location of the FPGAs.


This command is to confirm the pin mapping.

To use these blocks, right click after selecting all the blocks and make subsystem of them and put the subsystem wherever you want to use with any Simulink model. 

The block is now ready to use for the NMM.

Wednesday, April 15, 2015

Network on Chip and Its Topologies

Network on chip is a communication subsystem on a chip. NoC is the blend of network theory and methods for the communication on the chip. Mainly NoC is used in large VLSI systems for communication purposes. Public transportation Network is used for the transfer of information between various blocks in the network.

NoC is constructed by the combinations of the various Routers and Router play the most important role in the communication of the Network. The main message is delivering to the destination from the generating source by the help of the routers.


Router provides the Route for transferring the data from one block to block. It provides the exact controls to the Router so these controls can transfer the message or data.

Advantages of NoC:

There are many advantages of NoC. Some of them given below:

i)          The Communication channel of big design on single chip was very complex but by the help of the NoC it becomes easy to understand.
ii)           Reduction in physical area.

Parameters used to Measure the NoC performance:
  1.       Throughput 
  2.       Bandwidth
  3.       Latency
Throughput is the maximum traffic accepted by the network. 

The bandwidth refers to the maximum rate of data propagation. The measurement unit of bandwidth is bits per second.

Latency is the time among the beginning of the transmission of the data and its complete reception at the destination.

Various Topologies used in NoC:

Here Topology word is used to tell the type of the connection between the different routers.

i)                    2-D Grid:
The main connection for the Routers in the 2-D Grid Topology is shown in the below given diagram:

                                                          2-D Grid Topology network

ii)                  2-D Torus:

There are connected various Routers in the following figure.

2-D Torus Topology Connection

iii)                3-D Hypercube:

The routers connection for the 3-D hypercube topology is shown below:

                                     3-D Hypercube Topology Connection

iv)                Octagon:

The connection for the octagon topology is shown below. In this, routers are connected in the octagon pattern so called as the octagon topology.

                                       Octagon topology connection

v)                  Fat tree :

The connection of the Router for the Fat tree topology is shown below. This type of topology connection is indirect one.

Fat Tree

vi)                3-stage butterfly:

The connection for the 3 stage butterfly topology is shown below:

                                                    3-Stage Butterfly topology connection