DESIGN & COMPARISON OF CONVENTIONAL TPG & LP-TPG USING BRAUN ARRAY MULTIPLIER AS CIRCUIT UNDER TEST

Here, we are introducing a LP-TPG (i.e. Low Power Test Pattern Generator, using Low Frequency Shift Register). Also we’d designed a conventional TPG. Now we will use Braun Array Multiplier, using both Ripple carry adder as well as Kogge stone adder. Now in our design, we’ll use outputs of both the test pattern generators as an input to both kinds of multipliers. Our whole architecture has being designed and simulated using MODELSIM SE 6.5 & synthesised on XLINX ISE DESIGN SUITE 13.3. Till now, we are getting four simulation windows as shown below, according to our design model. Further we are trying to implement our whole design on another software QUARTUS II 13.1. So as to analysis that power consumption i.e. static power, dynamic power, on chip power, off chip power in case of LP-TPG will be less than conventional TPG.

 Author - Akash Kumar

       (Research Associate at Silicon Mentor)

Simulation window – Conventional TPG is connected to Braun Array Multiplier, using Ripple carry adder.

Simulation window – LP-TPG is connected to Braun Array Multiplier, using Ripple carry adder.

Simulation window – Conventional TPG is connected to Braun Array Multiplier, using Kogge stone adder

Simulation window – LP-TPG is connected to Braun Array Multiplier, using Kogge stone adder