Showing posts with label ieee news updates. Show all posts
Showing posts with label ieee news updates. Show all posts

Thursday, July 24, 2014

Static Vs Dynamic Logic Circuits

 Comparison Between Dynamic Logic Circuit & Static Logic Circuit


• Dynamic logic circuit requires small area in comparison of static logic circuits.

• Dynamic logic circuit generates smaller parasitic capacitance, due to the smaller area on
   silicon chip.

• These dynamic circuits has smaller dynamic power than static design because the less
   parasitic capacitance.

• The common clock system in dynamic circuits in all over the circuits enables the
   synchronization.

1) Static logic Gates: The output of these logic gates depends on its applied input levels.

The output can be keep as long as the power is supplied to circuit.

2) Dynamic Logic Gates: The output operation of these gates depends on the temporary

storage of the charge in the load capacitance. This stored charge does not stay for

indefinitely, it updates with the different voltage levels.
  
(Research Associate at Silicon Mentor)


Dynamic Logic Circuit








Static Logic Circuit





Friday, July 11, 2014

DESIGN & COMPARISON OF CONVENTIONAL TPG & LP-TPG USING BRAUN ARRAY MULTIPLIER AS CIRCUIT UNDER TEST

Here, we are introducing a LP-TPG (i.e. Low Power Test Pattern Generator, using Low Frequency Shift Register). Also we’d designed a conventional TPG. Now we will use Braun Array Multiplier, using both Ripple carry adder as well as Kogge stone adder. Now in our design, we’ll use outputs of both the test pattern generators as an input to both kinds of multipliers. Our whole architecture has being designed and simulated using MODELSIM SE 6.5 & synthesised on XLINX ISE DESIGN SUITE 13.3. Till now, we are getting four simulation windows as shown below, according to our design model. Further we are trying to implement our whole design on another software QUARTUS II 13.1. So as to analysis that power consumption i.e. static power, dynamic power, on chip power, off chip power in case of LP-TPG will be less than conventional TPG.

 Author - Akash Kumar
       (Research Associate at Silicon Mentor)


Simulation window – Conventional TPG is connected to Braun Array Multiplier, using Ripple carry adder.
Simulation window – LP-TPG is connected to Braun Array Multiplier, using Ripple carry adder.
Simulation window – Conventional TPG is connected to Braun Array Multiplier, using Kogge stone adder
Simulation window – LP-TPG is connected to Braun Array Multiplier, using Kogge stone adder


Tuesday, July 8, 2014

Need for IEEE VLSI Projects


IEEE (Institute of Electrical and Electronics Engineers) is an advanced innovation and technical group of engineers, scientists, developers, physicists, medical doctors and researchers around the world. It has established on 1st  January, 1963 with the merging of societies AIEE (American Institute of Electrical Engineers) and IRE (Institute of Radio Engineers). IEEE is the world’s largest technical professional association which has now many fields such as electronic, electrical, communication, computing, nanotechnology, bioengineering and robotics. Now IEEE serves 38 societies, transactions, 130 journals and 300 conferences anually. IEEE prefers exact experimental research in specific areas. Research is most important for the student, researcher, professor and engineer. Without research, all those has nothing new to deliver to the world. Studies after the graduation means research. 21st centuries research is mainly focused on electronics because modern technological world,involves electronics to make things smart and fast. VLSI (Very Large Scale Integration) is the core domain of electronic semiconductor circuits. IEEE research in VLSI is the need of electronic world. Electronics can not move further without a research in VLSI.So IEEE VLSI projects and research papers are needed for the M.Tech and Ph.D students. VLSI is most innovative and interesting field in electronics. VLSI has mainly two types of design steps: Frontend and Backend. In frontend, we design the system and RTL level using HDLs according to the specification of projects or IC and in backend, we design logic, circuit and layout level of the projects. M.Tech, Ph.D and industrial VLSI projects should be new technological oriented to create new electronics world for the upcoming generation.

           Author - Deepak Berwal
           (Research associate at Silicon Mentor)




Click on the links to get the following Projects list :  
  
VLSI projects       Antenna Projects             MATLAB Projects


Wednesday, July 2, 2014

Design a Single Precision Floating Point Unit

A single precision floating point unit in verilog is introduced. The novelty of a single precision floating point unit is to provide five arithmetic operations: addition, subtraction, multiplication, division, and square root. In top-down design approach, four arithmetic modules: addition/subtraction, multiplication, division, and square root are combined to form a single precision floating point unit. Each module is independent from each other. The modules are realized and validated using verilog simulation in the Modelsim SE 6.5 and synthesis using Xlinx ISE Design Suite 13.3.

The single precision floating point unit implemented, is a 32-bits processing unit which allows arithmetic operations on a floating point numbers. The floating point unit complies fully with IEEE 754 standard.

Author - Akash Kumar 
(Research Associate at SiliconMentor)

single precision Floating Point