How to Design and simulate a NAND gate in HSPICE

From the inverter, let’s move to the NAND gate. Being one of the universal gates, NAND gate holds utmost importance in any logic design

  NAND gate in HSPICE

Fig.  Shown on the top is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high.

An advantage of CMOS over NMOS is that both low-to-high and high-to-low output transitions are fast since the pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

Netlist 

*CMOS 2-INPUT NAND GATE

vdd 1 0 5
v1 4 0 pulse(0 3.3 0 1ps 1ps 500ns 1000ns)
v2 3 0 pulse(0 3.3 0 1ps 1ps 1000ns 2000ns)
m1 2 4 1 1 pmos1 w=13u l=3u
m2 2 3 1 1 pmos1 w=13u l=3u
m3 2 4 5 0 nmos1 w=8u l=3u
m4 5 3 0 0 nmos1 w=8u l=3u

*NMOS Device

.model nmos1 nmos (LEVEL=2, UO=150, VTO=1.4581, GAMMA=1.8658, PHI=0.7974,
+ KP=1.0354e-5, LAMBDA=0.02, XJ=0.2u, LD=0.2u, PB=0.9939,
+ NSUB=5e16, NSS=2e10, TOX=50n, TPG=+1)

*PMOS Device

.model pmos1 pmos (LEVEL=2, UO=316.67, VTO=-1.5488, GAMMA=1.8658, PHI=0.7974,
+ KP=2.1860e-5, LAMBDA=0.02, XJ=0.2u, LD=0.2u, PB=0.9939,
+ NSUB=5e16, NSS=2e10, TOX=50nm, TPG=+1)
.trans 1ns 5400ns 0.1ns
.probe
.end

                                       

Tags : NAND gate      NMOS          CMOS       NMOS          PMOS           SPICE Training

Author - Amresh Kumar Singh

(Trainee Engineer at Silicon Mentor)