Low Power Techniques in the FINFET

Fin type field effect transistors (FINFETs) is a new type of CMOS in VLSI. These are doubled gated device. The two gates of a FINFET can either be shorted or independently controlled for lower leakage. It has lower short channel effects (SCEs) and ideal sub threshold voltage. To make a FINFET, the front oxide is made much thicker than the side oxides in order to effectively deactivate the front gate. We call this device FINFET because the thin channel region stands vertically similar to the fin between the sources and drain regions.

There are different modes of FINFET (a) Short gate (SG) mode (b) Independent gate (IG) mode (c) Low power (LP) mode (d) A hybrid IG/LP-mode.

1.   SG Mode:In this mode both gate are shorted and we get good control over the channel length
2.   IG Mode:In this independent signals are provided to the two device gates, this will reduce the number of transistors in the circuit.
3.   LP mode:In this we are applying a low voltage to n type FINFET and high voltage to P type FINFET.
4.   Hybrid mode:It is a combination of LP and IG modes.

Different techniques for low power consumption:

a)DTCMOS: This technique reduces standby power by using the P-MOS switch with higher threshold voltage in between power supply and the circuit. It can also use N-MOS switches with higher threshold voltage in between ground and the circuit. This high threshold transistors can operate with high speed and low switching power dissipation. When the circuit is in OFF mode the high threshold transistors are turned OFF causing reduction in the sub-threshold leakage current.

b)Self Controlled Voltage Level(SVL): There are three types of SVL techniques:

•          Type-1 has an upper SVL circuit, in this we can use single P-MOS switch and n no. of N-MOS switches connected in series. The ON P-MOS connects a power supply and the load circuit in the active mode and the all N-MOS are disconnected and they are in standby mode.
•          Type-2 has a lower SVL circuit, in which we use single N-MOS switch and n no. of P-MOS switches connected in series. The lower SVL circuit not only supplies 0 to the active-load circuit through the ON N-MOS but also supplies 0 to the standby load circuit through the use of the ON P-MOS.
•          Type-3 has a combination of lower and upper SVL circuit.When the gate voltage of circuit is kept at 0, the P-MOS is turned ON while the N-MOS is turned OFF. The current is pass through the P-MOS and through the n P-MOS in the lower circuit. When control signal turns to 1 the N-MOS is turned ON and turns OFF P-MOS, power is supplied to the circuit through n N-MOS. This results in a decrease in the sub threshold current of the N-MOS that is the leakage current through the circuit decreases.

Hardware Co-simulation for Non Memory Mapped Ports using Simulink and System Generator

Hardware or FPGA is a primary requirement for any real time implementation of mathematical algorithms. The main drawback of the process is the limited resources and the interfaces available on the FPGA for the co-simulation process. One of the main highlighted concern is the mapping of the peripheral ports on the FPGA with the algorithm. 

Co-simulation is the best process to use for the real time implementation of the algorithms because the process facilitates the features of the two tools simultaneously. MATLAB is known as the best tool for the implementation of the mathematical algorithms for a number of applications. The other tool System Generator from by the Xilinx is known best for the hardware implementation of the algorithms. 

Both the tools work together simultaneously to real time implementation of the mathematical algorithms on the FPGAs. The complications are their when you want to use the LEDs, Buttons or other output devices. To resolve these problems we manually create the Non Memory Mapped Ports according to the steps given below.

To manually create NMM we need these different Simulink and system generator block sets.

1.       In1

2.       Convert

3.       Gateway In

4.       Out1

5.       Terminator

To generate the library subsystem we have to put these block as in the given fig:1

Fig: 1

The work is almost done we just need to run the given three command on the MATLAB command window after selecting the “Gateway Out” block

>>xlSetNonMemMap(gcbh, 'Xilinx', 'ethernetcosim'); 

>>xlSetPortParams(gcbh, 'IOConstraint', 'NET "pmod0" LOC = U18;');

This command is to map output of the design to the LED of the FPGA. “U18” is the pin location of the LED<0> in our case and can be changed on the basis of different pin location of the FPGAs.

>>dump(xlGetPortParams(gcbh));

This command is to confirm the pin mapping.

To use these blocks, right click after selecting all the blocks and make subsystem of them and put the subsystem wherever you want to use with any Simulink model. 

The block is now ready to use for the NMM.

Bio-Medical Signal Processing at a Glance

ECG signal:

ECG signal, also known as EKG signal, is a diagnostic tool which makes the electrical and muscular function of the heart accessible for analysis. The continuous pumping of blood by heart from lungs to various parts of body is responsible for generation of ECG signal.  The heart is a two stage electrical pump and its electrical activity can be measured by placing the electrodes on the chest or by using some special bands. The electrocardiogram is used to measure the rate and rhythm of the heartbeat, as well as it provides an evidence of blood flow to the heart muscles.

                              

                                                                                       Fig1 ECG signal

Introduction:

For ECG signal analysis we perform Signal Processing on it. With the help of the signal processing we can extract that information from the ECG signal that we cannot extract by simply visualizing it. Many noises may add into our ECG signal and elimination of these noises is also the important objective of the Signal processing. And another main objective of the signal processing is to do the compression of the data. The following diagram shows the algorithm for basic ECG signal processing:

             

                                                          Fig2 Algorithm for basic ECG signal processing

After getting the information by the signal processing, we can use this information in many applications.

ECG Pre-Processing:

Filtering is done in Pre-Processing part of the ECG signal and after filtering, various analyses are performed on the ECG signal. Filters are mainly designed for the removal of the following:

• 1      Baseline wander

• 2      Power line interference

Baseline wander:

The main factor require for designing the linear, time-invariant, high pass filters for removal of baseline wander is cutoff frequency and phase response characteristics In definite situations, baseline wander becomes commonly well-defined at higher heart rates such as during the final stages of a stress test when the workload increases. Then, it may be advantageous to couple the cut-off frequency to the general heart rate, rather than to the lowest possible heart rate, to further improve baseline removal.

Figure 3(a) shows Electrocardiographic baseline wander because of sudden body movements. The amplitude of the baseline wander is considerably larger than that of the QRS complexes .Figure3(b)  a close-up in time (10 x) of the ECG signal framed in (a)

Power line Interference:

Electromagnetic fields generated by a power line signify a common noise source in the ECG that is characterize by 50 or 60 Hz sinusoidal interference, probably accompany by a number of harmonics. Such narrow band noise makes the analysis and interpretation of the ECG more difficult, as the description of low-amplitude waveforms becomes unpredictable and fake waveforms may be introduced.

4 QRS Detection:

The information content present in any ECG signal is its existence and its time of occurrence. The QRS complex present in ECG signal indicates the existence of beat in the signal. Also many other analyses of human body like pulse rate, blood pressure measurement, physical and mental status etc can be performed after detection of QRS peak. Thus, proper detection is of utmost requirement which ensures that refined and distortion less signal will be further used by system for human body analysis. The poor detection can lead to limitation in performance of whole system.

The two problems frequently faced in QRS detection are that the signal either remains undetected or signal is detected falsely. The problem of more concern is no detection, because the information content from that part is lost and cannot be recovered in later stages of the system. For false detection of signal, there are various methods to resolve it like performing classification of QRS morphologies. The detector must be capable of detecting different morphologies to allow sudden changes in the output i.e. it should not lock onto certain types of rhythm, but treat each event as if it could occur at almost any time. The noises also accompany the detected signal. These noises may be transient in behavior or persistent. 

                                     

                                                          Fig Block diagram of QRS Detector

The above figure shows the block diagram of a commonly used QRS detector. The input to system is the ECG signal, and the output is a series of occurrence times of the QRS complex signal. It is a must requirement to improve the resolution using an algorithm which is responsible for time alignment of the detected signal. Time alignment helps in elimination of smearing which occurs during computation of the ensemble average of several detected beats.