How to make an FPGA Partially Reconfigurable

Partially reconfiguration means changing the FPGA partially or only the selected part of the FPGA is reconfigured. It can be done in two ways:

i)    Module based partial reconfiguration
Partial reconfiguration on the basis of difference

Module based partial reconfiguration:

In module based reconfiguration we reconfigure on the specific module or only by changing a selected module we can do the partially reconfiguration of our FPGA. The portions of the design to be reconfigured are known as reconfigurable modules. Specific properties and specific layout criteria must be met with respect to a reconfigurable module, FPGA design intending to use partial reconfiguration must be planned and laid out with that in mind.

Partial reconfiguration on the basis of difference:

Partial reconfiguration on the basis of difference is a method of making small changes in an FPGA design, such as changing I/O standards, LUT equations, and block RAM content.

Applications:

i)    To lessen power or making the design power-efficient.
ii)    Through the JTRS Program, SDRs are becoming a reality for the defense industries as an effective and necessary tool for communication. SDRs assure the JTRS standard by having both a software-reprogrammable operating environment and the ability to support multiple channels and networks simultaneously.
iii)    Partial reconfiguration is useful in a variety of applications across many industries. The aerospace and defense industries have certainly taken advantage of its capabilities.
iv)    Increased system performance. Although a portion of the design is being reconfigured, the rest of the system can keep on to operate. There is no loss of performance or functionality with unaffected portions of a design.
v)    Hardware sharing. Because partial reconfiguration allows you to run multiple applications on a single FPGA, hardware sharing is realized. Benefits include reduced device count, reduced power consumption, smaller boards, and in particular lower costs.

key steps used in Xilinx to make the FPGA partially Reconfigured:

1: First Create Processor Hardware System.
2: Then Create Software Project.
3: After then Create a Plan ahead Project.
4: Defining a Reconfigurable Partition.
5: Adding Reconfigurable Modules.
6: significant the Reconfigurable Partition Region.
7: Running the Design Rule Checker.
 8: Then Create the First Configuration, Implementing, and Promoting.
9: Then Create Other Configurations, and Implementing.
10: Then Run Partial Reconfiguration to Verify Utility.
11: Generating Bit Files.
12: Creating an Image, and Testing.

Advantages:

There are many advantages to make the FPGA reconfigured. only some from them are following:

I)    To make the device more efficient.
II)    To lessen the LUTs of the design by replacing only specific portion.
III)    To lessen power of the design by replacing only specific portion.
IV)    To lessen the delay of the design by replacing only specific portion or a specific module.




                                                                                                                   
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Low Power Techniques in the FINFET

Fin type field effect transistors (FINFETs) is a new type of CMOS in VLSI. These are doubled gated device. The two gates of a FINFET can either be shorted or independently controlled for lower leakage. It has lower short channel effects (SCEs) and ideal sub threshold voltage. To make a FINFET, the front oxide is made much thicker than the side oxides in order to effectively deactivate the front gate. We call this device FINFET because the thin channel region stands vertically similar to the fin between the sources and drain regions.

There are different modes of FINFET (a) Short gate (SG) mode (b) Independent gate (IG) mode (c) Low power (LP) mode (d) A hybrid IG/LP-mode.

1.   SG Mode:In this mode both gate are shorted and we get good control over the channel length
2.   IG Mode:In this independent signals are provided to the two device gates, this will reduce the number of transistors in the circuit.
3.   LP mode:In this we are applying a low voltage to n type FINFET and high voltage to P type FINFET.
4.   Hybrid mode:It is a combination of LP and IG modes.

Different techniques for low power consumption:

a)DTCMOS: This technique reduces standby power by using the P-MOS switch with higher threshold voltage in between power supply and the circuit. It can also use N-MOS switches with higher threshold voltage in between ground and the circuit. This high threshold transistors can operate with high speed and low switching power dissipation. When the circuit is in OFF mode the high threshold transistors are turned OFF causing reduction in the sub-threshold leakage current.

b)Self Controlled Voltage Level(SVL): There are three types of SVL techniques:

•          Type-1 has an upper SVL circuit, in this we can use single P-MOS switch and n no. of N-MOS switches connected in series. The ON P-MOS connects a power supply and the load circuit in the active mode and the all N-MOS are disconnected and they are in standby mode.
•          Type-2 has a lower SVL circuit, in which we use single N-MOS switch and n no. of P-MOS switches connected in series. The lower SVL circuit not only supplies 0 to the active-load circuit through the ON N-MOS but also supplies 0 to the standby load circuit through the use of the ON P-MOS.
•          Type-3 has a combination of lower and upper SVL circuit.When the gate voltage of circuit is kept at 0, the P-MOS is turned ON while the N-MOS is turned OFF. The current is pass through the P-MOS and through the n P-MOS in the lower circuit. When control signal turns to 1 the N-MOS is turned ON and turns OFF P-MOS, power is supplied to the circuit through n N-MOS. This results in a decrease in the sub threshold current of the N-MOS that is the leakage current through the circuit decreases.

An Introduction to CNN: Carrying the Machine learning on its shoulders

Traditional neural network layers use a matrix multiplication to describe the interaction between each input unit and each output unit. This means every output unit interacts with every input unit. Convolutional networks, however, typically have sparse interactions. This is accomplished by making the kernel smaller than the input and using it for the whole image.

Parameter sharing concept is used in CNN. It refers to using the same parameter for more than one function (input values) in a model. In a convolutional neural net, each member of the kernel is used at every position of the input. The parameter sharing used by the convolution operation means that rather than learning a separate set of parameters for every location, we learn only one set. This is also called as sparse connectivity.

If the function that a layer needs to learn is indeed a local, translation invariant function, then the layer will be dramatically more efficient if it uses convolution rather than matrix multiplication. If the necessary function does not have these properties, then using a convolutional layer will cause the model to have high training error.

Pooling

First stage, the layer performs several convolutions in parallel to produce a set of presynaptic activations. In the second stage, each presynaptic activation is run through a nonlinear activation function, such as the rectified linear activation function. This stage is sometimes called the detector stage. In the third stage, we use a pooling function. A pooling function replaces the output of the net at a certain location with a summary statistic of the nearby outputs. For example, the max pooling operation reports the maximum output within a rectangular neighborhood. Pooling helps to make the representation becomes invariant to small translations of the input.

Zero-padding

Zero-padding setting is when just enough zero-padding is added to keep the size of the output equal to the size of the input. It calls same convolution, full convolution, in which enough zeroes are added for every pixel to be visited k times in each direction.

The CNN behavior analysis will be explained in the further articles from the R&D team at SiliconMentor working in Computer Vision, Biomedical Signal Analysis, VLSI and their associated domains.

Hardware Implementation of Image Processing Algorithms

Digital image processing is done to improve the quality of images. The images are processed and enhanced in order to obtain the required information from it. It is an ever expanding field with a number of applications in medicine, space, art, meteorology, etc. Hardware implementation of digital image processing techniques is very commonly done using Verilog-HDL or VHDL gives a logical explanation of any circuit which can be further developed and tested. The main advantage of using HDLs is that any logical input can be simulated on FPGA (Hardware implementation).Application specific hardware implementation offers much greater speed than a software implementation.

Advancements in VLSI technology have made this hardware implementation an attractive, feasible and less time consuming task to undergo.  FPGA is one of the best technologies available for hardware design  because their structure is able to exploit spatial and temporal parallelism .FPGAs are ideal in many embedded systems applications because of their small size, low power consumption ,a number of input-output  ports and logic blocks. Also FPGAs are reprogrammable chips, hence are very versatile to be used.

Algorithms can be implemented in Verilog HDL using Xilinx ISE, MATLAB and MODEL SIM. Hardware implementation of Verilog codes provides us with the ability to verify the logical codes simulated using software. Hardware implementation helps in the co-simulation of the already simulated logic. It helps the designer to reformulate the algorithm.

It provides us an overlook of the way the respective logical circuit will work when brought to real life applications. Also, an idea of the market need of the circuit and how it will actually work, is provided by hardware implementation. The use of reconfigurable hardware to implement algorithms for image processing minimizes the time-to-market cost, provides prototyping and debugging.

Therefore, the reconfigurable devices like FPGA seem to be the ideal choice for implementation of image processing algorithms. SiliconMentor is a team with expertise in the fields both software implementation and hardware prototyping. The team focuses to provide a shared platform for the researchers and innovators by providing guidance in the specified areas.

Importance of Research Paper Publication in Your PhD Research

On internet you can find a million of research papers on different topics of the world. The topics can be related to different research areas such as Engineering, Science, arts or any other topic which can contribute in the advancement of the world in respective areas. Whenever a student enters in Second year or third year of their bachelor education, their mentors start to suggest them to publish their work. In the same scenario Master and PhD level students also publish research papers. Therefore the question arise why should we publish our research? This article is focused on importance of research paper publication in PhD and concludes pint wise the importance of research paper publication in PhD. PhD students usually begin their course to earn title ‘Dr’ in front of their name but after some time they realize that to earn a PhD degree they all need to publish more and more high quality research papers at national as well as international level.

This Research publication during PhD helps them in following ways:

•          Research paper publication is important if somebody wants to remain in academia after completion of the PhD.

•          Every university has their unique procedure to award PhD to their students. The usual process is to submit thesis but in some of the universities PhD students can submit few good quality published research papers instead of PhD thesis.

•          The high quality research papers during PhD helps recruiters to select the best PhD scholars for future academic or researcher position.

•          A high quality research paper helps PhD scholars to stand out from the group of ordinary researchers.

The importance of research paper publication can also be understood using an example. Let us suppose an academic or industrial organization want to test or measure the researcher reputation in national as well as international level for hiring or funding purpose. 

In that case the organization may pursue the following procedure.

•          The number of research papers and the quality.

•          The impact of research in terms of number of citations.

•          National and international level research papers.

•          National and international level research funding received.

There are many more factors for which a PhD scholar should publish a research paper anybody can explore it at Silicon Mentor.