Friday, July 3, 2015

FPGA Design and Verilog HDL Projects List

1.      FPGA implementation of LDPC bit-flipping algorithm using Co-simulation.
2.      FPGA implementation of LDPC Decoder using min-sum algorithm.
3.      Implementation of AES for image encryption and decryption.
4.      Development and verification of SPI protocol.
5.      Development and verification of PPI protocol.
6.      Audio processing using digital filter using Co-simulation.
7.      Design of single precision (32-bit) Floating point ALU.
8.      Design and implementation of the 128-point FFT processor.
9.      Design and implementation of 16bit RISC Processor.
10.    FPGA implementation of the 12-bit Ternary multiplier.
11.    Design of ECG signal processing and denoising using co-simulation.
12.    Design of low power test pattern generator.
13.    A BIST TPG for Low Power Dissipation and High Fault Coverage
14.    Low-Transition LFSR for BIST-Based Applications
15.    Verilog Implementation of UART with BIST capability
16.    Verilog implementation of RSA cryptography algorithm.
17.    Verilog implementation of 64, 32, 16 and 8 bit CSA.
18.    Design of low power TPG using LP_LFSR for fault coverage.
19.    Design and implementation of the 32-point FFT processor by Folding Transform.
20.    FPGA implementation of the REDEYE detection and correction.
21.    FPGA implementation JPEG 2000 using 2-D DWT .
22.    Hardware implementation JPEG 2000 using DWT.
23.    Hardware implementation of the H.264 encoder for HD Video.
24.    Hardware implementation of the MPEG encoder.
25.    FPGA implementation of Quantization algorithms for multi standard video platform.
26.    FPGA implementation of the motion object detection based on background subtraction.
27.    FPGA implementation of the AES algorithm for reduced cycles.
28.    Design and implementation of the MRI image enhancement and denoising.
29.    Hardware implementation of the ECG (Arrhythmia).
30.    Fault tolerant deflecting router with high fault coverage for ON-Chip network.
31.    BIST implementation of the UART.
32.    Orientation field estimation for the fingerprint enhancement.
33.    Verilog implementation of Reconfigurable router (NOC).
34.    Verilog implementation of Decimal to binary conversion.
35.    Verilog implementation of 3D-DWT.

If you need any suggestion or research guidance for FPGA design & verilog HDL projects then feel free to contact us.

No comments:

Post a Comment