Low Power Digital VLSI Projects List

• ALU in FINFET
• VARIABLE TAPER CMOS BUFFER DESIGN
• Sleepy Keeper Approach for Power Performance Tuning in VLSI Design.
• 0-9 bit pattern recognition circuits using neural network, 3-bit pattern recognition.
• An adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage Scalable Standard Cell Library.
• Lewis grey comparator.
• 4×4-Bit Array Two Phase Clocked Adiabatic Static CMOS Logic Multiplier with New XOR.
• Adiabatic Logic Based Low Power Multiplexer and De-multiplexer.
• Low Power D-latch design using MCML Tri-state Buffers.
• Ultra Low Power NAND Based Multiplexer and Flip flop.
• MOS Current Mode Logic Realization of Digital Arithmetic Circuits.
• 0-0\9 digit pattern recognition circuit using neural network.
• 6 transistors XOR and XNOR using FINFET.
• Winner Take All Circuits of O (n) Complexity.
• Low power adiabatic booth multiplier using Positive feedback adiabatic logic (PFAL).
• Transmission gate based full adder in deep sub-micron technology.
• Low power radix-4 booth multiplier using GDI logic.
• High performance nibble multiplexer using modified adiabatic logic.
• Sense energy recovery full adder working in sub-threshold region of operation.
• Clock gated 4-bit Johnson counter using low power JK flip flop.
• A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs.
• New Low-Power Techniques: Leakage Feedback with Stack & Sleep Stack with Keeper.
• Low Power, Delay Optimized Buffer Design using 70 nm CMOS Technology.
• Clock gated 4-bit Johnson counter using low power JK flip flop.
• Design of a novel low power 8-transistor 1-bit full adder cell.

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