Digital Signal Processing on FPGA

Digital signal processing is the most challenging field of research. It has replaced the conventional analog signal processing with an advantage of low error probability and high SNR. Digital signal processing adds high speed processing capabilities to the system with an overhead of analog to digital and digital to analog conversions. FPGA (field programming gate array) has bough revolution in signal processing system development due to its parallel implementation capabilities with throughput in multiple Gigabits/sec.

FPGAs are best suited not only for combination or sequential logic implementation; these are optimum for high speed signal processing as well. PhD or M.Tech scholars can carry their research in DSP a step further by implementing their designs in real time using DSP oriented FPGAs. The DSP slices and dedicated blocks on FPGA accelerate performance of FPGAs and makes system development easy and accurate.

A brief idea of design flow used for DSP system is:

•          system modeling on Simulink
•          simulation (with floating point data)
•          Data type conversion (to fixed point)
•          Hardware implementation and simulation

System modeling is the first step in design of system where behavioral blocks, transforms, delay elements etc. are used to model the Digital Signal Processing system which is then verified for desired performance. Till now the data types used are of floating point precision. To implement this on hardware we need to convert this system to work on fixed point data types so that the system can be implemented on hardware efficiently. The width of coefficient is quantized and fixed in this process. Now the design is written in HDL and mapped to hardware. The hardware is then simulated to check the performance with quantized coefficients and fixed word lengths. If the performance is satisfactory the design is finalized otherwise the conversion is carried out again.

WHAT ARE DIFFERENT CMOS POWER REDUCTION TECHNIQUES?

As the technology continues to scale down to the deep submicron process, leakage power consumption has become a major concern in designing CMOS VLSI circuits because of reduced threshold voltage and device geometry.

MTCMOS (Multiple Threshold CMOS)- It is a variation of CMOS chip technology in which transistors are there with multiple threshold voltages (V_th) for the purpose of reducing delay and power in circuits. In order to minimize clock periods on critical delay paths, low threshold (V_th) devices are used as they switch faster, but the problem with low V_th devices is that they have substantially high leakage power. In order to minimize static leakage power high V_th devices are used on non-critical paths. Sleep Transistors technique is used in MTCMOS for reducing power. When fast switching speed is required than low V_th devices are used. High V_th devices are turned on inactive mode and off in sleep mode.

Fig1: MTCMOS Circuit

Power Gating- In this technique power consumption is reduced, by not passing currents to those blocks that are not in use. In low threshold transistors sub-threshold leakage current is more, so in order to suppress the high subthreshold leakage current, high sub-threshold voltage switches are added between the low threshold voltage logic circuits and the power supply and ground lines. These high threshold voltages power supply and ground switches are controlled by a sleep signal. During active mode, these switches are on, providing virtual power and ground lines for the logic circuits and during standby mode, these switches are off to reduce sub-threshold leakage current.

DTCMOS (Dual Threshold CMOS)- In this technology high threshold transistor are applied on non-critical path to reduce the sub-threshold leakage and performance is maintained by low threshold transistors in critical paths. So no additional transistors are required and performance as well as low power can be achieved simultaneously.