HOW TO SELECT ARCHITECTURE FOR IMAGE PROCESSING ON FPGA

Implementation of real time image processing on serial general purpose processors is hard to achieve. This is due to the limited resources, general purpose architecture and large data set presented by image. For example if we have to perform single operation on every pixel of the 640x480 gray scale frame from input video source at 30 frames per second, it will require the serial processor to perform 1.84 million operations per second excluding the operations required for reading from and writing data to buffers. This demands a very high throughput serial processor (GPP). 

The above stated problem of image processing at real time can be countered by using FPGAs by using their inherent parallelism of hardware which is an advantage over the fetch decode architecture of processor. Along with solutions comes the complexity of implementation. The software algorithms developed for general purpose processors cannot be directly implemented on FPGA and need to be converted to take advantage of parallelism and meet the constraints implied by hardware. There are popular ways to implement software image processing codes in high level languages (HLL) to FPGA.

• Using HLL to HDL compilers
• Manual conversion

The cases where the hardware implementation is functionally equivalent to software implementation, the mapping is easy and compilers can be used efficiently. Sometimes standard algorithm made for software is not compatible for hardware due to reasons like, the implementation requires too many resources or accesses memory in a way which the hardware cannot support. In such cases we need to re write the algorithm in hardware keeping in mind the limitations and constrains of hardware.

The major constraints implied by hardware implementation are:

•  Timing
• Bandwidth
• Resource utilization and conflict 

The affect of these constraints is closely dependent on the processing model adopted for implementation of the application. The general processing models used are: 

• Stream
• Offline
• Hybrid processing

In stream processing the design samples incoming data like raster scan and perform as much operations as possible. In this mode the role of memory is very important and the processing speed is dependent on bandwidth of memory.

Offline processing doesn’t imply much constraints and it is most suitable for direct mapping of software based algorithm. Hybrid processing is mixture of stream and offline processing and the timing constraints re relaxed as the image is sampled at slower rate.

WHAT ARE DIFFERENT CMOS POWER REDUCTION TECHNIQUES?

As the technology continues to scale down to the deep submicron process, leakage power consumption has become a major concern in designing CMOS VLSI circuits because of reduced threshold voltage and device geometry.

MTCMOS (Multiple Threshold CMOS)- It is a variation of CMOS chip technology in which transistors are there with multiple threshold voltages (V_th) for the purpose of reducing delay and power in circuits. In order to minimize clock periods on critical delay paths, low threshold (V_th) devices are used as they switch faster, but the problem with low V_th devices is that they have substantially high leakage power. In order to minimize static leakage power high V_th devices are used on non-critical paths. Sleep Transistors technique is used in MTCMOS for reducing power. When fast switching speed is required than low V_th devices are used. High V_th devices are turned on inactive mode and off in sleep mode.

Fig1: MTCMOS Circuit

Power Gating- In this technique power consumption is reduced, by not passing currents to those blocks that are not in use. In low threshold transistors sub-threshold leakage current is more, so in order to suppress the high subthreshold leakage current, high sub-threshold voltage switches are added between the low threshold voltage logic circuits and the power supply and ground lines. These high threshold voltages power supply and ground switches are controlled by a sleep signal. During active mode, these switches are on, providing virtual power and ground lines for the logic circuits and during standby mode, these switches are off to reduce sub-threshold leakage current.

DTCMOS (Dual Threshold CMOS)- In this technology high threshold transistor are applied on non-critical path to reduce the sub-threshold leakage and performance is maintained by low threshold transistors in critical paths. So no additional transistors are required and performance as well as low power can be achieved simultaneously. 

What is Run Length coding in Video Compression ?

Video compression technologies are about reducing and removing redundant video data so that a digital video file can be effectively sent over a network. With efficient compression techniques, a significant reduction in file size can be achieved with little or no adverse effect on the visual quality. The video quality can be affected if the file size is further lowered by raising the compression level for a given compression technique.

Run length coding is the video compression method sometimes called as Run Length used in video processing. It is also used in many image formats. The role of RLE is to reduce data redundancy. It is based on the repetition of consecutive elements. The basic principle is to replace the sequence of the same symbol by a number of its occurrences. Thus, according to this principle, “HHHHHYYYYYYYYYYYYYY” when compressed yields “5H14Y”. The compression gain is thus (19-5)/19, that is, approximately 73.7 %. Run length coding is lossless compression, because all the information is retained after decoding. 

Generally RLE is used after quantization. RLE step re-arranges the quantized data in a format that reduces data redundancy in bit stream. For run length encoding, the 8x8 block should be scanned into 64-entry array in a zigzag fashion, as shown in figure1.

Figure1: Zigzag scanning

The block, which has now become a 64 entry, should next be manipulated using a modified run-length encoding algorithm transforming it into a series of integer pairs consisting of a run component and a signed level component. The run integer represents the number of zero entries preceding a level value in the array. The final run of zero entries in the array ends at the 64^th block entry and not with a signed level- this reality is encoded as End of Block. The syntax as shown in Figure2.

Figure 2: Sample block Run length coding.

                                                                                                      Author - Hemika Yadav

                                                                                Intern Design Engineer at Silicon Mentor)