WHAT ARE DIFFERENT CMOS POWER REDUCTION TECHNIQUES?

As the technology continues to scale down to the deep submicron process, leakage power consumption has become a major concern in designing CMOS VLSI circuits because of reduced threshold voltage and device geometry.

MTCMOS (Multiple Threshold CMOS)- It is a variation of CMOS chip technology in which transistors are there with multiple threshold voltages (V_th) for the purpose of reducing delay and power in circuits. In order to minimize clock periods on critical delay paths, low threshold (V_th) devices are used as they switch faster, but the problem with low V_th devices is that they have substantially high leakage power. In order to minimize static leakage power high V_th devices are used on non-critical paths. Sleep Transistors technique is used in MTCMOS for reducing power. When fast switching speed is required than low V_th devices are used. High V_th devices are turned on inactive mode and off in sleep mode.

Fig1: MTCMOS Circuit

Power Gating- In this technique power consumption is reduced, by not passing currents to those blocks that are not in use. In low threshold transistors sub-threshold leakage current is more, so in order to suppress the high subthreshold leakage current, high sub-threshold voltage switches are added between the low threshold voltage logic circuits and the power supply and ground lines. These high threshold voltages power supply and ground switches are controlled by a sleep signal. During active mode, these switches are on, providing virtual power and ground lines for the logic circuits and during standby mode, these switches are off to reduce sub-threshold leakage current.

DTCMOS (Dual Threshold CMOS)- In this technology high threshold transistor are applied on non-critical path to reduce the sub-threshold leakage and performance is maintained by low threshold transistors in critical paths. So no additional transistors are required and performance as well as low power can be achieved simultaneously. 

VLSI ieee projects 2014 guidance and support

Silicon mentor is a hub to guide & backup the Mtech. and PhD students at the time of pursuing their major & mini projects in semiconductor and communication domain. we boost the students in thesis preparation and provide a technical platform for research in the era of VLSI,Embedded Systems, Communication, Semiconductor, Biology and Technology Interface and Electrical and Electronics. Students may also reach us if they are willing for industrial tool specifications such as cadence orcad,Xilinx FPGA implementation(VHDL Verilog HDL),Tanner EDA,Advance Design System(ADS),AVR studio,MATLAB,H-spice,P-spice,Modelism,Network simulator2,Proteaus and many more to follow. Major projects in VLSI & ECE.

The focus research area in which Silicon Mentor provide services is Neural Network, DSP, Video processing, Advance Analog, Low Power Circuit Technique, Standard cell ( Sub-threshold ).

VLSI Projects : Basically VLSI has two phases i.e. Front End & Back End. 

VLSI Front End Projects: Front End includes the digital designing,RTL design(Register Transfer Level),simulation and Design Under Test(DUT) techniques.It consist of various key terms such as verilog,system verilog,SVA,OVM,UVM,PERL,TCL etc. It comprises of concepts like clock,setup & hold time,FSM and RTL optimization. It uses tools like Questa Sim,Modelism,GTK wave,Xilinx,Icarves Verilog. 

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PROCESS CORNERS

Process corners refer to the process inaccuracies, temperature and other parameter variations. The simulations that are used to analyze these process inaccuracies are different from each other. The corners describe the differences of a chip behavior form its nominal condition are usually supplied with the process kit and these are originally located in model libraries.

These kit contains  corner condition for the SS, FF, TT, FS, SF etc process, where these abbreviations stands for Slow NMOS-Slow PMOS, Fast NMOS-Fast PMOS, Typical NMOS-Typical PMOS, Fast NMOS-Slow PMOS, Slow NMOS-Fast PMOS etc. These corner conditions are checked with the help of EDA or simulation process and in result it describes IC behavior. It may contain the process of temperature variation and V_dd (supply voltage) variation depends on customer IC requirement. e.g. For car manufacturing company the IC should be checked for  maximum corner conditions and temperature variations otherwise  IC will not fulfill all requirement.­­­

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Power dissipation in CMOS digital circuits

The growing development of CMOS logic VLSI circuits has decreased the circuit size, increased the switching speed , there is one problem associated with this technology that is known as the power dissipation . There are many researchers who are trying to decrease the power consumption of CMOS based digital circuits. The main cause of power dissipation in CMOS based VLSI circuits are divided on the basis of   its working or behavior.

There are mainly two cases of Power dissipation 1) Dynamic power dissipation 2) Static power dissipation. This dynamic power dissipation can be further divided in three parts known as switching power dissipation, short circuit power dissipation and glitching power dissipation. These can be reduced by changing the parameters of the following models:

  switching power

P _switching = α F_operating.V_dd² C_L [for full output swing]

Where F_operating is operating frequency_, V_dd = supply voltage_, C_L= Net load capacitance_, α= switching activity factor of gate.

P _switching = α F_operating V_dd. V_swing C_L [for low voltage swing]

Short circuit power

Pshort circuit = (μC_ox/12) (W/L)(V_dd-2V_th)³τ F_operating

Where  τ = rise/ fall time of the input signal

The static power dissipation occurs because of two reasons: DC current and Transistor leakage current.

   

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