Monday, August 18, 2014

An Introduction to Vedic Mathematics

Vedic mathematics is the ancient name of mathematics that was rediscovered in twentieth century. Vedic Mathematics has a unique technique of calculations based on 16 Sutras.  

A simple digital multiplier (referred henceforth as Vedic multiplier) architecture based on the Urdhva Triyakbhyam (means vertically and Cross wise) Sutra is explained. Urdhva – Triyakbhyam is the general formula which is applicable to all cases of multiplication.

The beauty of Vedic multiplier is that here partial product generation and additions are done concurrently or simultaneously. Hence, it is well adapted to parallel processing. The feature makes it more attractive for binary multiplications. This in turn reduces delay and reduces complex calculations into simple one. In most of the dsp applications, the critical operations are multiplication and accumulation.

The method is explained below for two, 2 bit numbers A and B where A = a1a0 and B = b1b0. Firstly, the least significant bits are multiplied which gives the least significant bit of the final product (vertical). Then, the LSB of the multiplicand is multiplied with the next higher bit of the multiplier and added with, the product of LSB of multiplier and next higher bit of the multiplicand (crosswise). The sum gives second bit of the final product and the carry is added with the partial product obtained by multiplying the most significant bits to give the sum and carry. The sum is the third corresponding bit and carry becomes the fourth bit of the final product. The 2X2 Vedic multiplier module is implemented by four input AND gates & two half-adders.
method for 4x4 Vedic multiplier  

It is found that the hardware architecture of 2x2 bit Vedic multiplier is same as the hardware architecture of 2x2 bit conventional Array Multiplier.
Hence it is concluded that multiplication of 2 bit binary numbers by Vedic method does not made significant effect in improvement of the multiplier’s efficiency. The 4x4 bit Vedic multiplier module is implemented using four 2x2 bit Vedic multiplier modules as shown above. 
In 4x4 multiplications, A= a3 a2 a1 a0 and B= b3 b2 b1 b0. The output line for the multiplication result is – s7s6s5s4 s3s2 s1 s0 and carry is ca2ca3.The main advantage behind this architecture is that the area needed for Vedic multiplier is very small as compared to other multiplier architecture. 

hardware architecture of 4x4 multiplier

Tags : Vedic mathematics     Vedic Multiplier      Vedic Methods    Introduction to Vedic Mathematics

Author - Hemika Yadav
(Intern at Silicon Mentor)

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