PROCESS CORNERS

Process corners refer to the process inaccuracies, temperature and other parameter variations. The simulations that are used to analyze these process inaccuracies are different from each other. The corners describe the differences of a chip behavior form its nominal condition are usually supplied with the process kit and these are originally located in model libraries.

These kit contains  corner condition for the SS, FF, TT, FS, SF etc process, where these abbreviations stands for Slow NMOS-Slow PMOS, Fast NMOS-Fast PMOS, Typical NMOS-Typical PMOS, Fast NMOS-Slow PMOS, Slow NMOS-Fast PMOS etc. These corner conditions are checked with the help of EDA or simulation process and in result it describes IC behavior. It may contain the process of temperature variation and V_dd (supply voltage) variation depends on customer IC requirement. e.g. For car manufacturing company the IC should be checked for  maximum corner conditions and temperature variations otherwise  IC will not fulfill all requirement.­­­

mtech. vlsi projects, mtech projects for ece, mtech projects, mtech. paper publication, m.tech research projects, m.tech ieee projects

Levels Of IC Design

The design of integrated circuits (IC) contains the different levels of abstraction . According to the IC design standards we can study the complex circuits at following four levels.

1). Device Physics Level  2). Transistor Level  3). Architecture Level  4). System Level

1). The device physics level describes the device internal behaviour for electric field and charge.

2). Transistor level consist of a group of these devices .

3). Architectural level defines a unit of several building blocks to perform a certain functions.

3). System level consist of the set of subsystems.e.g.  ADC, DAC etc.

In conclusion  one may say that in today's IC industry above four levels are essential to achieve a high performance and low cost device. 

                                                

                                                          

Mtech projects, Vlsi designing institute in india, mtech. Paper publication, mtech. Projects guidance,  M.tech Research projects, ieee projects, ieee projects for ece

Power dissipation in CMOS digital circuits

The growing development of CMOS logic VLSI circuits has decreased the circuit size, increased the switching speed , there is one problem associated with this technology that is known as the power dissipation . There are many researchers who are trying to decrease the power consumption of CMOS based digital circuits. The main cause of power dissipation in CMOS based VLSI circuits are divided on the basis of   its working or behavior.

There are mainly two cases of Power dissipation 1) Dynamic power dissipation 2) Static power dissipation. This dynamic power dissipation can be further divided in three parts known as switching power dissipation, short circuit power dissipation and glitching power dissipation. These can be reduced by changing the parameters of the following models:

  switching power

P _switching = α F_operating.V_dd² C_L [for full output swing]

Where F_operating is operating frequency_, V_dd = supply voltage_, C_L= Net load capacitance_, α= switching activity factor of gate.

P _switching = α F_operating V_dd. V_swing C_L [for low voltage swing]

Short circuit power

Pshort circuit = (μC_ox/12) (W/L)(V_dd-2V_th)³τ F_operating

Where  τ = rise/ fall time of the input signal

The static power dissipation occurs because of two reasons: DC current and Transistor leakage current.

   

 mtech. Vlsi projects Mtech projects for ece Mtech projects mtech. Paper publication

mtech. Projects guidance M.tech Research projects ieee projects M.tech ieee projects